公开(公告)号：US20090101989A1

公开(公告)日：2009-04-23

申请号：US11874385

申请日：2007-10-18

申请人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L27/06 ,  H01L21/3205

CPC分类号： H01L27/0617 ,  H01L23/5256 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

公开(公告)号：US20080308900A1

公开(公告)日：2008-12-18

申请号：US11761403

申请日：2007-06-12

申请人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

发明人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L29/00 ,  G03F1/00

CPC分类号： G03F1/40 ,  G03F1/36

摘要： A photolithography mask contains at least one sublithographic assist feature (SLAF) such that the image of the fuselink shape on a photoresist contains a constructive interference portion and two neck portions. The width of the constructive interference portion is substantially the same as a critical dimension of the lithography tool and the widths of the two neck portions are sublithographic dimensions. The image on a photoresist is subsequently transferred into an underlying semiconductor layer to form an electrical fuse. The fuselink contains a constructive interference portion having a first width which is substantially the same as the critical dimension of the lithography tool and two neck portions having sublithographic widths. The inventive electrical fuse may be programmed with less voltage bias, current, and energy compared to prior art electrical fuses.

摘要翻译： 光刻掩模包含至少一个亚光刻辅助特征（SLAF），使得光致抗蚀剂上的熔体形状的图像包含相长的干涉部分和两个颈部。 构造干涉部分的宽度基本上与光刻工具的临界尺寸相同，并且两个颈部的宽度是亚光刻尺寸。 随后将光致抗蚀剂上的图像转移到下面的半导体层中以形成电熔丝。 熔丝包含具有与光刻工具的临界尺寸基本相同的第一宽度和具有亚光刻宽度的两个颈部的构造干涉部分。 与现有技术的电熔丝相比，本发明的电熔丝可被编程为具有更少的电压偏置，电流和能量。

公开(公告)号：US20080157216A1

公开(公告)日：2008-07-03

申请号：US11619357

申请日：2007-01-03

申请人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

发明人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

IPC分类号： H01L27/092 ,  H01L21/762

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

公开(公告)号：US20070235792A1

公开(公告)日：2007-10-11

申请号：US11566360

申请日：2006-12-04

申请人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Ho ,  Babar Khan ,  Deok-kee Kim

发明人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Ho ,  Babar Khan ,  Deok-kee Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/10888

摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

摘要翻译： 衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO） 沟槽的顶部并且在字线的方向上延伸超过沟槽。 以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

公开(公告)号：US07153737B2

公开(公告)日：2006-12-26

申请号：US10905684

申请日：2005-01-17

申请人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Babar Ali Khan ,  Deok-kee Kim

发明人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Babar Ali Khan ,  Deok-kee Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10888

摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

摘要翻译： 衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO） 沟槽的顶部并且在字线的方向上延伸超过沟槽。 以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。