公开(公告)号：US08163640B2

公开(公告)日：2012-04-24

申请号：US11874385

申请日：2007-10-18

申请人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L27/06 ,  H01L21/3205

CPC分类号： H01L27/0617 ,  H01L23/5256 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

公开(公告)号：US20090101989A1

公开(公告)日：2009-04-23

申请号：US11874385

申请日：2007-10-18

申请人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L27/06 ,  H01L21/3205

CPC分类号： H01L27/0617 ,  H01L23/5256 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

公开(公告)号：US07479689B2

公开(公告)日：2009-01-20

申请号：US11627384

申请日：2007-01-26

申请人： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

发明人： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

IPC分类号： H01L23/58

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronically programmable fuse (e-fuse) is disclosed. In one embodiment, the e-fuse includes a cathode surrounded only by silicon dioxide; an anode; and a polysilicon-silicide programmable link coupling the anode and the cathode, wherein the anode and the polysilicon-silicide programmable link are surrounded by a low dielectric constant (low-k) material on a top and a side thereof.

摘要翻译： 公开了一种电子可编程保险丝（e-fuse）。 在一个实施例中，电熔丝包括仅被二氧化硅包围的阴极; 阳极; 以及耦合所述阳极和所述阴极的多晶硅硅化物可编程链路，其中所述阳极和所述多晶硅硅化物可编程链路被其顶部和侧面上的低介电常数（低k）材料围绕。

公开(公告)号：US20080179706A1

公开(公告)日：2008-07-31

申请号：US11627384

申请日：2007-01-26

申请人： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

发明人： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronically programmable fuse (e-fuse) is disclosed. In one embodiment, the e-fuse includes a cathode surrounded only by silicon dioxide; an anode; and a polysilicon-silicide programmable link coupling the anode and the cathode, wherein the anode and the polysilicon-silicide programmable link are surrounded by a low dielectric constant (low-k) material on a top and a side thereof.

摘要翻译： 公开了一种电子可编程保险丝（e-fuse）。 在一个实施例中，电熔丝包括仅被二氧化硅包围的阴极; 阳极; 以及耦合所述阳极和所述阴极的多晶硅硅化物可编程链路，其中所述阳极和所述多晶硅硅化物可编程链路被其顶部和侧面上的低介电常数（低k）材料围绕。

公开(公告)号：US20080122026A1

公开(公告)日：2008-05-29

申请号：US11564344

申请日：2006-11-29

申请人： Xiangdong Chen ,  Deok-Kee Kim ,  Haining Yang

发明人： Xiangdong Chen ,  Deok-Kee Kim ,  Haining Yang

IPC分类号： H01L29/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is directed to an improved eFUSE that prevent rupturing of the fuse link, reduces current through the fuse link, and optimizes electromigration through the fuse link through the use of a feedback circuit.

摘要翻译： 本发明涉及一种改进的eFUSE，其防止熔丝链断裂，减少通过熔丝链的电流，并且通过使用反馈电路优化通过熔断体的电迁移。

公开(公告)号：US09082751B2

公开(公告)日：2015-07-14

申请号：US13232737

申请日：2011-09-14

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/4236 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/7835 ,  H01L29/785

摘要： According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

摘要翻译： 根据一个实施例，半FinFET半导体器件包括形成在半导体本体上的栅极结构。 半导体本体包括源极区域，该区域包括延伸超过栅极结构的第一侧面的多个鳍片，以及与栅极结构的与多个鳍片相对的第二侧相邻的连续漏极区域。 连续漏极区域使得半FinFET半导体器件具有降低的导通电阻。 一种制造具有半FinFET结构的半导体器件的方法包括：在半导体本体中指定源极和漏极区域，蚀刻源极区域以产生多个源极鳍片，同时在蚀刻期间掩蔽漏极区域以提供连续的漏极区域， 从而导致半FinFET结构具有降低的导通电阻。

公开(公告)号：US09041171B2

公开(公告)日：2015-05-26

申请号：US13340430

申请日：2011-12-29

申请人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： H01L21/326 ,  H01L23/495 ,  H05K1/11 ,  B82Y99/00 ,  H01L23/498 ,  H05K1/02 ,  H01L21/48 ,  H05K3/40

CPC分类号： H01L23/49827 ,  B82Y10/00 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/029 ,  H05K3/4038 ,  H05K2201/0248 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/10378 ,  H05K2203/104 ,  H05K2203/105

摘要： An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

摘要翻译： 本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。 响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。 导电颗粒可具有导电外表面。 此外，导电粒子可以是球形的。 导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

公开(公告)号：US08659081B2

公开(公告)日：2014-02-25

申请号：US13613864

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08493767B2

公开(公告)日：2013-07-23

申请号：US13252880

申请日：2011-10-04

申请人： Akira Ito ,  Xiangdong Chen

发明人： Akira Ito ,  Xiangdong Chen

IPC分类号： G11C17/00 ,  H01L23/52

CPC分类号： H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

摘要翻译： 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

公开(公告)号：US08455977B2

公开(公告)日：2013-06-04

申请号：US13466986

申请日：2012-05-08

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

摘要翻译： 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。