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17 条记录 (耗时 0.014 秒)

    DRAM with schottky barrier FET and MIM trench capacitor
    1.
    发明授权
    DRAM with schottky barrier FET and MIM trench capacitor 有权
    具有肖特基势垒FET和MIM沟槽电容器的DRAM

    公开(公告)号：US08343864B2

    公开(公告)日：2013-01-01

    申请号：US13073103

    申请日：2011-03-28

    申请人： Puneet Goyal ,  Herbert Lei Ho ,  Pradeep Jana ,  Jin Liu

    发明人： Puneet Goyal ,  Herbert Lei Ho ,  Pradeep Jana ,  Jin Liu

    IPC分类号： H01L29/28 ,  H01L29/40 ,  H01L29/47

    CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/10867 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

    摘要： A semiconductor circuit and method of fabrication is disclosed. In one embodiment, the semiconductor circuit comprises a metal-insulator-metal trench capacitor in a silicon substrate. A field effect transistor is disposed on the silicon substrate adjacent to the metal-insulator-metal trench capacitor, and a silicide region is disposed between the field effect transistor and the metal-insulator-metal trench capacitor. Electrical connectivity between the transistor and capacitor is achieved without the need for a buried strap.

    摘要翻译： 公开了半导体电路和制造方法。 在一个实施例中，半导体电路在硅衬底中包括金属 - 绝缘体 - 金属沟槽电容器。 在与金属 - 绝缘体 - 金属沟槽电容器相邻的硅衬底上设置场效应晶体管，并且在场效应晶体管和金属 - 绝缘体 - 金属沟槽电容器之间设置硅化物区域。 实现晶体管和电容器之间的电连接，而不需要埋入带。

    Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same
    2.
    发明授权
    Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same 失效
    与中间线金属触点集成的沟槽金属 - 绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US07682896B2

    公开(公告)日：2010-03-23

    申请号：US11750355

    申请日：2007-05-18

    申请人： Herbert Lei Ho ,  Subramanian Srikanteswara Iyer ,  Vidhya Ramachandran

    发明人： Herbert Lei Ho ,  Subramanian Srikanteswara Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L21/8242 ,  H01L21/331

    CPC分类号： H01L27/10861 ,  H01L28/91 ,  H01L29/945

    摘要： The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material. The semiconductor device contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region.

    摘要翻译： 本发明涉及一种制造工艺的方法，该方法将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。 半导体器件包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选地至少一个场效应晶体管（FET）。 沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。

    Method for patterning a silicon-on-insulator photomask
    3.
    发明授权
    Method for patterning a silicon-on-insulator photomask 失效

    公开(公告)号：US06553561B2

    公开(公告)日：2003-04-22

    申请号：US09920688

    申请日：2001-08-02

    申请人： Karen Ann Bard ,  Herbert Lei Ho

    发明人： Karen Ann Bard ,  Herbert Lei Ho

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068

    摘要： A method for generating a patterned SOI photomask used for embedded DRAMs is described. The method systematically identifies embedded DRAM areas to be excluded from the SOI process and generates the shapes to be printed on the photomask so that the embedded DRAM may be fabricated on bulk silicon. The method includes the steps of: identifying and sorting DRAM array well shapes by common electrical net, resulting in a single array well shape for each electrical net (i.e., embedded DRAM cell). Next, all the n-band contacts touching a given array well shape are collected. These shapes are merged by common electrical net. A shape is then generated which is the smallest enclosing rectangle of the common electrical net of the n-band contact shapes. This represents the patterned SOI shape and defines the bulk areas onto which the embedded DRAM is to be built. Accordingly, the embedded DRAM macro is constructed in bulk areas while the logic is constructed in SOI.

    Self-aligned, silicided, trench-based DRAM/eDRAM processes with improved retention
    7.
    发明授权
    Self-aligned, silicided, trench-based DRAM/eDRAM processes with improved retention 失效
    自对准，硅化，基于沟槽的DRAM / eDRAM工艺，具有更好的保留性

    公开(公告)号：US07564086B2

    公开(公告)日：2009-07-21

    申请号：US11566360

    申请日：2006-12-04

    申请人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Ali Babar Khan ,  Deok-kee Kim

    发明人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Ali Babar Khan ,  Deok-kee Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L27/10867 ,  H01L27/10888

    摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

    摘要翻译： 衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO） 沟槽的顶部并且在字线的方向上延伸超过沟槽。 以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

    Self-aligned, silicided, trench-based, DRAM/EDRAM processes with improved retention
    9.
    发明授权
    Self-aligned, silicided, trench-based, DRAM/EDRAM processes with improved retention 有权
    自对准，硅化，基于沟槽的DRAM / EDRAM工艺，具有更好的保留性

    公开(公告)号：US07153737B2

    公开(公告)日：2006-12-26

    申请号：US10905684

    申请日：2005-01-17

    申请人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Babar Ali Khan ,  Deok-kee Kim

    发明人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Babar Ali Khan ,  Deok-kee Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L27/10888

    摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

    摘要翻译： 衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO） 沟槽的顶部并且在字线的方向上延伸超过沟槽。 以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。