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    DUAL STRESS STI
    1.
    发明申请
    DUAL STRESS STI 有权
    双重压力

    公开(公告)号：US20080157216A1

    公开(公告)日：2008-07-03

    申请号：US11619357

    申请日：2007-01-03

    申请人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    发明人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    IPC分类号： H01L27/092 ,  H01L21/762

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

    摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

    摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

    Dual stress STI
    2.
    发明授权
    Dual stress STI 有权
    双重应激STI

    公开(公告)号：US07521763B2

    公开(公告)日：2009-04-21

    申请号：US11619357

    申请日：2007-01-03

    申请人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    发明人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L31/00 ,  H01L29/00 ,  H01L23/34

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

    摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.

    摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

    Dual stress STI
    3.
    发明授权
    Dual stress STI 有权
    双重应激STI

    公开(公告)号：US07927968B2

    公开(公告)日：2011-04-19

    申请号：US12125106

    申请日：2008-05-22

    申请人： Deok-Kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    发明人： Deok-Kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

    摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

    摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

    Dual Stress STI
    4.
    发明申请
    Dual Stress STI 有权
    双重应力STI

    公开(公告)号：US20080220587A1

    公开(公告)日：2008-09-11

    申请号：US12125106

    申请日：2008-05-22

    申请人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    发明人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    IPC分类号： H01L21/762

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

    摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

    摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

    Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance
    5.
    发明授权
    Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance 有权
    形成具有低接触电阻的硅化源极/漏极触点的场效应晶体管的方法

    公开(公告)号：US07863201B2

    公开(公告)日：2011-01-04

    申请号：US12402816

    申请日：2009-03-12

    申请人： Yong-Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    发明人： Yong-Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/00

    CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

    摘要翻译： 根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。 在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。 通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。 这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。 该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

    Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance
    6.
    发明申请
    Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance 有权
    形成具有低接触电阻的硅化源/漏极触点的场效应晶体管的方法

    公开(公告)号：US20090239344A1

    公开(公告)日：2009-09-24

    申请号：US12402816

    申请日：2009-03-12

    申请人： Yong Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    发明人： Yong Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    IPC分类号： H01L21/335 ,  H01L21/28

    CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

    摘要翻译： 根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。 在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。 通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。 这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。 该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

    Asymmetric source/drain junctions for low power silicon on insulator devices
    7.
    发明授权
    Asymmetric source/drain junctions for low power silicon on insulator devices 有权
    低功率硅绝缘体器件的不对称源极/漏极结

    公开(公告)号：US08299509B2

    公开(公告)日：2012-10-30

    申请号：US13078476

    申请日：2011-04-01

    申请人： Seong-Dong Kim ,  Zhijong Luo ,  Huilong Zhu

    发明人： Seong-Dong Kim ,  Zhijong Luo ,  Huilong Zhu

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

    摘要： A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.

    摘要翻译： 半导体器件包括形成在本体衬底上的掩埋绝缘体层; 形成在所述掩埋绝缘体层上并对应于场效应晶体管（FET）的体区的第一类型半导体材料; 形成在所述掩埋绝缘体层上，邻近所述本体区域的相对侧并且对应于所述FET的源极和漏极区域的第二类型的半导体材料; 所述第二类型的半导体材料具有与所述第一类型的半导体材料不同的带隙; 其中FET的源极p / n结基本上位于具有较低带隙的第一和第二类型的半导体材料中的任何一个中，并且FET的漏极侧p / n结基本上完全位于 第一和第二类型的具有较高带隙的半导体材料。

    Transmitter and Transmitting Method Thereof In Wireless Communication System
    8.
    发明申请
    Transmitter and Transmitting Method Thereof In Wireless Communication System 有权
    无线通信系统中的发射机和发射方法

    公开(公告)号：US20090054013A1

    公开(公告)日：2009-02-26

    申请号：US11847763

    申请日：2007-08-30

    申请人： Hae-Moon Seo ,  Yeon-Kuk Moon ,  Young-Kuk Park ,  Kwang-Ho Won ,  Seong-Dong Kim

    发明人： Hae-Moon Seo ,  Yeon-Kuk Moon ,  Young-Kuk Park ,  Kwang-Ho Won ,  Seong-Dong Kim

    IPC分类号： H04B1/02

    CPC分类号： H04B1/0483

    摘要： A transmitter and a transmitting method of a wireless communication system are provided. The transmitter transmits RF signals using an outphasing scheme of converting one analog IF NC-EMS into two analog C-EMSs. In the transmitter, a baseband processor generates a baseband digital modulated I-signal and a baseband digital modulated Q-signal. A signal converter converts the baseband digital modulated I-signal and the baseband digital modulated Q-signal into a baseband analog modulated I-signal and a baseband analog modulated Q-signal. An IF processor up-converts the baseband analog modulated I-signal and the baseband analog modulated Q-signal to generate one analog IF NC-EMS. A signal component separator separates the analog IF NC-EMS into a first analog IF C-EMS and a second analog IF C-EMS. An RF processor up-converts the first analog IF C-EMS and the second analog IF C-EMS to generate a first analog RF C-EMS and a second analog RF C-EMS. A power amplifier amplifies powers of the first and second analog RF C-EMSs. An RF combiner combines the first and second analog RF C-EMSs having the amplified powers to generate one combined analog RF C-EMS.

    摘要翻译： 提供了一种无线通信系统的发射机和发射方法。 发射机使用将一个模拟IF NC-EMS转换成两个模拟C-EMS的外部方案来发射RF信号。 在发射机中，基带处理器产生基带数字调制I信号和基带数字调制Q信号。 信号转换器将基带数字调制I信号和基带数字调制Q信号转换成基带模拟调制I信号和基带模拟调制Q信号。 IF处理器对基带模拟调制信号和基带模拟调制Q信号进行升压转换，以生成一个模拟IF NC-EMS。 信号分量分离器将模拟IF NC-EMS分为第一模拟IF C-EMS和第二模拟IF C-EMS。 RF处理器将第一个模拟IF C-EMS和第二个模拟IF C-EMS升级转换，生成第一个模拟RF C-EMS和第二个模拟RF C-EMS。 功率放大器放大第一和第二模拟RF C-EMS的功率。 RF组合器组合具有放大功率的第一和第二模拟RF C-EMS以产生一个组合的模拟RF C-EMS。

    ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES
    9.
    发明申请
    ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES 有权
    用于绝缘子器件上的低功率硅的不对称源/漏极连接

    公开(公告)号：US20110180852A1

    公开(公告)日：2011-07-28

    申请号：US13078476

    申请日：2011-04-01

    申请人： Seong-Dong Kim ,  Zhijiong Luo ,  Huilong Zhu

    发明人： Seong-Dong Kim ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H01L29/772

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

    摘要： A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.

    摘要翻译： 半导体器件包括形成在本体衬底上的掩埋绝缘体层; 形成在所述掩埋绝缘体层上并对应于场效应晶体管（FET）的体区的第一类型半导体材料; 形成在所述掩埋绝缘体层上，邻近所述本体区域的相对侧并且对应于所述FET的源极和漏极区域的第二类型的半导体材料; 所述第二类型的半导体材料具有与所述第一类型的半导体材料不同的带隙; 其中FET的源极p / n结基本上位于具有较低带隙的第一和第二类型的半导体材料中的任何一个中，并且FET的漏极侧p / n结基本上完全位于 第一和第二类型的具有较高带隙的半导体材料。

    Real-time wireless sensor network protocol having linear configuration
    10.
    发明授权
    Real-time wireless sensor network protocol having linear configuration 有权
    具有线性配置的实时无线传感器网络协议

    公开(公告)号：US07885251B2

    公开(公告)日：2011-02-08

    申请号：US11316712

    申请日：2005-12-27

    申请人： Jae-Ho Kim ,  Sang-Shin Lee ,  Il-Yeup Ahn ,  Kwang-Ho Won ,  Seong-Dong Kim

    发明人： Jae-Ho Kim ,  Sang-Shin Lee ,  Il-Yeup Ahn ,  Kwang-Ho Won ,  Seong-Dong Kim

    IPC分类号： H04J3/06

    CPC分类号： B61L27/0088 ,  H04J3/0652 ,  H04J3/0655 ,  H04W56/00 ,  Y02D70/142

    摘要： A network configuration method of a sensor network configured to collect sensed data from a plurality of sensor nodes comprising: arranging linearly a path of respective node so as to enable all sensor nodes except for a sink node and a terminal node to have respectively a predecessor and a successor; and setting the time synchronization of whole network by fixing the each node take its own time synchronization on the basis of an operation section of the predecessor.

    摘要翻译： 传感器网络的网络配置方法，其被配置为从多个传感器节点收集感测数据，包括：线性地布置各个节点的路径，以便能够使得除了节点和终端节点之外的所有传感器节点分别具有前导和 继任者 并且通过固定每个节点在前一个操作部分的基础上进行自己的时间同步来设置整个网络的时间同步。