公开(公告)号：US07869266B2

公开(公告)日：2011-01-11

申请号：US12255624

申请日：2008-10-21

Applicant: Rajiv Yadav Ranjan ,  Roger Klas Malmhall ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Roger Klas Malmhall ,  Parviz Keshtbod

IPC: G11C11/00 ,  G11C11/14

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US20080225585A1

公开(公告)日：2008-09-18

申请号：US11860467

申请日：2007-09-24

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/15

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

Abstract: An embodiment of the present invention includes a multi-state current-switching magnetic memory element having a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

Abstract translation: 本发明的实施例包括具有磁隧道结（MTJ）的多状态电流切换磁存储元件，用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

公开(公告)号：US06404246B1

公开(公告)日：2002-06-11

申请号：US09741971

申请日：2000-12-20

Applicant: Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

IPC: H03L706

CPC classification number: H03L7/18 ,  H03K3/0231 ,  H03L7/087

Abstract: A system and method of generating an output signal of very precise frequency without the use of a crystal oscillator. An input signal is generated using any convenient such as an RC oscillator. A circuit for producing a frequency-controlled output signal comprises a phase lock loop having a VCO and a down counter. The down counter reduces the frequency of a VCO clock signal in accordance with a down count value. The down count value is loaded in a register and stored in non-volatile memory. The down count value is set during a calibration operation using a precision external clock signal. In this way, a clock signal with a highly precise frequency is generated without using a crystal oscillator.

Abstract translation: 一种在不使用晶体振荡器的情况下产生非常精确频率的输出信号的系统和方法。 使用任何方便的RC振荡器产生输入信号。 用于产生频率控制的输出信号的电路包括具有VCO和向下计数器的锁相环。 下降计数器根据递减计数值降低VCO时钟信号的频率。 递减计数值加载到寄存器中并存储在非易失性存储器中。 在使用精密外部时钟信号的校准操作期间设置递减计数值。 以这种方式，在不使用晶体振荡器的情况下产生具有高精度频率的时钟信号。

公开(公告)号：US4608585A

公开(公告)日：1986-08-26

申请号：US403694

申请日：1982-07-30

Applicant: Parviz Keshtbod

Inventor： Parviz Keshtbod

IPC: H01L27/112 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/50

CPC classification number: G11C16/0441 ,  H01L29/7883 ,  H01L27/115

Abstract: In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell. However, during erase, very efficient tunneling occurs from the floating gate to the substrate and the threshold voltage level decreases to a negative value. The difference between positive and negative values of the threshold voltage is comparable to that of conventional memory cells.

Abstract translation: 在依赖于通过薄氧化层的隧穿作用以在浮动栅极上存储电荷的类型的EEPROM存储器单元中，浮置栅极和存储单元的沟道区域被提供与衬底中相同类型的额外掺杂 以便将存储器单元的处女状态阈值电压提高到高的正值，例如4伏特。 此外，控制栅极和浮置栅极之间的重叠区域减小到在编程期间浮置栅极和控制栅极之间的电容基本上等于浮置栅极和衬底之间的电容，但是在编程期间的有效电容 在擦除模式期间浮动栅极和衬底大大减小。 结果，在编程期间很少或没有隧道发生，并且阈值电压电平与存储器单元的处女阈值相同。 然而，在擦除期间，从浮置栅极到衬底发生非常有效的隧穿，并且阈值电压电平降低到负值。 阈值电压的正值和负值之间的差异与常规存储器单元的差值相当。

公开(公告)号：US4527255A

公开(公告)日：1985-07-02

申请号：US395531

申请日：1982-07-06

Applicant: Parviz Keshtbod

Inventor： Parviz Keshtbod

IPC: G11C14/00 ,  G11C11/40

CPC classification number: G11C14/00 ,  Y10S257/904

Abstract: A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

Abstract translation: 非易失性存储单元（20）包含一对交叉耦合的类似极性FET（Q1和Q2），其用作用于存储数据位和类似极性的可变阈值绝缘栅的易失性位置（​​21） 用作非易失性存储位置（22）的FET（Q3）。 可变阈值FET的源极耦合到交叉耦合FET中的一个的漏极，其绝缘栅电极耦合到交叉耦合FET的另一个的漏极，其漏极耦合到电源。 一对阻抗元件（R1和R2）分别耦合在交叉耦合FET的漏极之间，另一方面则耦合在电源上。 在电源关闭之前，导致数据位蒸发，电源被脉冲到适当的电平，以使该位被传送到非易失性位置。 当电源恢复到正常电平时，原始数据位自动返回到易失性位置。