公开(公告)号：US08574928B2

公开(公告)日：2013-11-05

申请号：US13443818

申请日：2012-04-10

Applicant: Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Abstract translation: 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US20130244344A1

公开(公告)日：2013-09-19

申请号：US13610587

申请日：2012-09-11

Applicant: Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

Inventor： Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L27/228

Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Abstract translation: 描述了使用两个正交线图案化步骤制造MTJ阵列的方法。 描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。 在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模 通过所有的MTJ单元层的层和下层形成完整的MTJ柱。 在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

公开(公告)号：US08488376B2

公开(公告)日：2013-07-16

申请号：US13476879

申请日：2012-05-21

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/14

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。

公开(公告)号：US08477529B2

公开(公告)日：2013-07-02

申请号：US13623054

申请日：2012-09-19

Applicant: Parviz Keshtbod ,  Ebrahim Abedifard

Inventor： Parviz Keshtbod ,  Ebrahim Abedifard

IPC: G11C11/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US20130088915A1

公开(公告)日：2013-04-11

申请号：US13475814

申请日：2012-05-18

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/14 ,  H01L29/82

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

公开(公告)号：US20130087870A1

公开(公告)日：2013-04-11

申请号：US13476904

申请日：2012-05-21

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: H01L29/82

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。

公开(公告)号：US08164947B2

公开(公告)日：2012-04-24

申请号：US12985028

申请日：2011-01-05

Applicant: Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US08148174B1

公开(公告)日：2012-04-03

申请号：US13100048

申请日：2011-05-03

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L43/12

Abstract: A method of manufacturing a magnetic memory element includes the steps of performing a first etching an oxide layer is etched, using a first photo-resist, the oxide layer formed on top of a contact layer that is formed on top of a magneto tunnel junction (MTJ), depositing a second photo-resist and second etching to leave a portion of the contact layer used to suitably connect the MTJ to circuits outside of the magnetic memory element.

Abstract translation: 一种制造磁存储元件的方法包括以下步骤：使用第一光致抗蚀剂进行第一蚀刻，蚀刻氧化层，形成在形成于磁隧道结顶部的接触层顶部上的氧化物层 沉积第二光刻胶和第二蚀刻以留下用于将MTJ适当地连接到磁存储元件外部的电路的接触层的一部分。

公开(公告)号：US20120002463A1

公开(公告)日：2012-01-05

申请号：US13235224

申请日：2011-09-16

Applicant: Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C11/14

CPC classification number: G11C11/1675 ,  B82Y10/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

公开(公告)号：US20110305078A1

公开(公告)日：2011-12-15

申请号：US13216997

申请日：2011-08-24

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/14 ,  H01L29/82

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。