公开(公告)号：US08073986B2

公开(公告)日：2011-12-06

申请号：US12782232

申请日：2010-05-18

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface by the identification circuitry. The controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.

Abstract translation: 具有存储器模块，接口，识别电路和耦合到存储器模块和识别电路的控制器的存储器件。 识别电路被配置为响应于先前通过识别电路施加到接口的多个信号，从在接口处感测到的多个信号中识别所选择的操作模式。 控制器可操作以响应于识别电路将存储器件配置为所选择的操作模式。

公开(公告)号：US20100228890A1

公开(公告)日：2010-09-09

申请号：US12782232

申请日：2010-05-18

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00 ,  G06F12/02

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface by the identification circuitry. The controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.

Abstract translation: 具有存储器模块，接口，识别电路和耦合到存储器模块和识别电路的控制器的存储器件。 识别电路被配置为响应于先前通过识别电路施加到接口的多个信号，从在接口处感测到的多个信号中识别所选择的操作模式。 控制器可操作以响应于识别电路将存储器件配置为所选择的操作模式。

公开(公告)号：US20090204750A1

公开(公告)日：2009-08-13

申请号：US12426662

申请日：2009-04-20

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/02

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US06912618B2

公开(公告)日：2005-06-28

申请号：US09850790

申请日：2001-05-07

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C16/08 ,  G11C16/10 ,  G11C29/00 ,  G06F12/00

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US06182162B2

公开(公告)日：2001-01-30

申请号：US09034173

申请日：1998-03-02

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F1300

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: An improved compact flash memory card system includes an improved compact flash memory card desktop adapter and an improved compact flash memory card. The improved compact flash memory card desktop adapter utilizes a fifty pin socket to interface with the compact flash memory card. The desktop adapter also utilizes a plug adapter to interface with a computer. For more efficient communication between the improved compact flash memory card and the computer, the improved desktop adapter adopts the universal serial bus architecture. The improved compact flash memory card utilizes a fifty pin connection to interface with a computer through an interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial bus mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with an interface device, this improved compact flash memory card automatically detects which operation mode is used by this interface device and configures the memory card to be compatible with the present operation mode. Because all fifty pins of the flash memory card are occupied to either transfer data or provide control signals to and from the flash memory card, this improved flash memory card merely senses selected pins to determine the present mode of operation.

Abstract translation: 改进的紧凑型闪存卡系统包括改进的紧凑型闪存卡桌面适配器和改进的紧凑型闪存卡。 改进的紧凑型闪存卡桌面适配器使用五十针插座与紧凑型闪存卡进行接口。 桌面适配器还使用插头适配器与计算机进行接口。 改进的紧凑型闪存卡和计算机之间的通信更为有效，改进的桌面适配器采用通用串行总线架构。 改进的紧凑型闪存卡利用五十针连接通过接口设备与计算机接口。 闪存卡的五十针连接可以在各种配置中使用，例如通用串行总线模式，PCMCIA模式和ATA IDE模式。 这些操作模式中的每一种都需要不同的协议。 在使用接口设备初始化时，该改进的紧凑型闪存卡自动检测该接口设备使用哪种操作模式，并将存储卡配置为与当前操作模式兼容。 因为闪存卡的所有五十个引脚都被占用以传输数据或向闪存卡提供控制信号，所以该改进的闪存卡仅仅感测所选择的引脚以确定当前的操作模式。

公开(公告)号：US5479638A

公开(公告)日：1995-12-26

申请号：US37893

申请日：1993-03-26

Applicant: Mahmud Assar ,  Siamack Nemazie ,  Petro Estakhri

Inventor： Mahmud Assar ,  Siamack Nemazie ,  Petro Estakhri

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/14

CPC classification number: G06F3/0601 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7211 ,  Y10S706/90

Abstract: A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoids an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit for evenly using all blocks in the mass storage is provided. These advantages are achieved through the use of several flags, a map to directly correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit.

Abstract translation: 半导体大容量存储装置可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，该装置避免擦除循环。 （擦除周期被理解为包括完全编程要擦除的块，然后擦除块）。通过将更改的数据文件编程为空的大容量存储块而不是将其自身作为硬盘来避免擦除周期。 定期地，大容量存储将需要清理。 其次，提供了用于均匀地使用大容量存储器中的所有块的电路。 这些优点通过使用几个标志来实现，地图将块的逻辑地址与该块的物理地址和每个块的计数寄存器直接相关。 特别地，为缺陷块，使用块，旧版块提供标志，确定块被擦除和写入和擦除禁止的次数的计数。

公开(公告)号：US08724413B2

公开(公告)日：2014-05-13

申请号：US13235224

申请日：2011-09-16

Applicant: Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C11/16 ,  G11C7/06 ,  G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C7/14 ,  G11C7/08

CPC classification number: G11C11/1675 ,  B82Y10/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract translation: 多状态电流切换磁存储元件包括由用于存储多于一位的信息的非磁性层分开的磁隧道结（MTJ）堆叠，其中施加到存储元件的不同电流电平导致切换到不同的 状态。

公开(公告)号：US08389301B2

公开(公告)日：2013-03-05

申请号：US13305668

申请日：2011-11-28

Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

Abstract translation: 非均匀开关型非易失性磁存储元件包括固定层，形成在固定层顶部上的阻挡层，形成在阻挡层顶部上的第一自由层，形成非均匀开关层（NSL） 在第一自由层的顶部和形成在不均匀开关层的顶部上的第二自由层。 在基本上垂直于固定层，阻挡层，第一自由层，不均匀的开关层和第二自由层的方向上施加开关电流，导致第一自由层，第二自由层和非自由层的状态之间的切换， 均匀的开关层，开关电流大大降低。

公开(公告)号：US20120170361A1

公开(公告)日：2012-07-05

申请号：US13345600

申请日：2012-01-06

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud ASSAR

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud ASSAR

IPC: G11C11/14

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract translation: 闪存RAM存储器包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器， 易失性RAM驻留在单片模具上。 非易失性RAM由以三维形式布置的磁存储单元堆叠形成，用于更高密度和更低成本。

公开(公告)号：US07721017B2

公开(公告)日：2010-05-18

申请号：US12199269

申请日：2008-08-27

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Apparatus and methods provide for configuring a peripheral device in response to applying defined sets of signals to input/output terminals of the peripheral device, sensing the signals at those input/output terminals after applying the defined sets of signals, and comparing the sensed signals with the defined sets of signals.

Abstract translation: 装置和方法提供用于响应于将定义的信号集合应用于外围设备的输入/输出端子来配置外围设备，在应用所定义的信号集之后感测那些输入/输出端子处的信号，并将感测信号与 定义的信号组。