公开(公告)号：US06201273B1

公开(公告)日：2001-03-13

申请号：US09225668

申请日：1999-01-05

申请人： Chen-Jong Wang ,  Mong-Song Liang

发明人： Chen-Jong Wang ,  Mong-Song Liang

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

摘要： A method and structure is described for a DRAM cell having a double wall tub shaped capacitor. The structure of the capacitor has two embodiments: a double wall tub shaped capacitor and a double wall cup shaped capacitor. In a first embodiment for the tub shaped capacitor, the method comprises using two masks to form a tub shaped hole partial through an insulating layer and a concentric contact hole over the source. A polysilicon layer is formed over the insulating layer. Oxide spacers are formed on the sidewalls of the tub shaped hole. The polysilicon layer is patterned to separate adjacent electrodes. Next, a polysilicon inner wall is formed on the spacer sidewalls. The oxide spacers are then removed. The dielectric and top electrode are formed next thus completing the double wall tub shaped capacitor. The second embodiment for forming the cup shaped capacitor comprises forming an insulating layer the substrate surface and forming a photoresist layer with an opening over a source region. The insulating layer is isotropically etched through the opening to form a cup shaped cavity. Next, the insulating layer is anisotropically etch through the opening to form a contact opening exposing the source. A polysilicon layer is formed filling the contact hole and the cup shaped cavity. Oxide and polysilicon spacers are sequentially formed on the sidewalls of the cylindrical hole. The insulating layer and oxide spacers are then removed. A capacitor dielectric and a top electrode are formed over the storage electrode to complete the double wall cup shaped capacitor.

摘要翻译： 描述了具有双壁桶形电容器的DRAM单元的方法和结构。 电容器的结构具有两个实施例：双壁桶状电容器和双壁杯形电容器。 在用于桶形电容器的第一实施例中，该方法包括使用两个掩模以在源极上部分地穿过绝缘层和同心接触孔形成盆形孔。 绝缘层上形成多晶硅层。 氧化物间隔件形成在桶形孔的侧壁上。 图案化多晶硅层以分离相邻的电极。 接下来，在间隔壁侧壁上形成多晶硅内壁。 然后除去氧化物间隔物。 接下来形成电介质和顶电极，从而完成双壁桶形电容器。 用于形成杯形电容器的第二实施例包括在衬底表面上形成绝缘层并在源极区域上形成具有开口的光致抗蚀剂层。 绝缘层通过开口进行各向同性蚀刻，形成杯形腔。 接下来，绝缘层通过开口各向异性地蚀刻以形成暴露源的接触开口。 形成填充接触孔和杯形腔的多晶硅层。 氧化物和多晶硅间隔物依次形成在圆柱形孔的侧壁上。 然后去除绝缘层和氧化物间隔物。 在存储电极上形成电容器电介质和顶电极以完成双壁杯形电容器。

公开(公告)号：US6136638A

公开(公告)日：2000-10-24

申请号：US195653

申请日：1998-11-19

申请人： Jin-Yuan Lee ,  Mong-Song Liang

发明人： Jin-Yuan Lee ,  Mong-Song Liang

IPC分类号： G11C11/4074 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/8242

CPC分类号： H01L27/10897 ,  G11C11/4074 ,  H01L21/823878 ,  G11C2207/104

摘要： Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the voltage levels created by the logic core. If the gate oxide has a thickness that is equal to the gate oxide thickness of the peripheral circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by peripheral circuits, and signal provided by the bit line voltage generator has voltage levels equal to those provided by logic circuits within the logic core. If the gate oxide has a thickness that is equal to the thickness of the gate oxide of the logic circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by the logic circuits, and the bit line voltage generator has voltage levels equal to those provided by the logic circuits.

公开(公告)号：US6110822A

公开(公告)日：2000-08-29

申请号：US47539

申请日：1998-03-25

申请人： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

发明人： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/44 ,  H01L21/00 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11 ,  H01L21/76838 ,  H01L27/1108 ,  H01L21/2022

摘要： A method of forming a contact in a thin film transistor with a gate electrode and an interconnect formed on a substrate, in an SRAM device comprises the following steps. Form a gate oxide layer over device. Form a split amorphous silicon layer over gate oxide layer. Form a cap layer over split amorphous silicon layer. Form a contact opening down to interconnect. Form contact metallization in opening on the surface of interconnect either as a blanket titanium layer followed by rapid thermal anneal to form a silicide and stripping unreacted titanium or by selective formation of a tungsten metal silicide in the opening. Strip cap layer from device. Form a second amorphous silicon layer on split silicon layer. Recrystallize silicon layers to form a polysilicon channel layer from amorphous silicon layers. Dope regions of polysilicon channel layer aside from a channel region above gate electrode.

摘要翻译： 在SRAM器件中，在具有形成在衬底上的栅极和互连的薄膜晶体管中形成接触的方法包括以下步骤。 在器件上形成栅氧化层。 在栅极氧化层上形成分裂的非晶硅层。 在分裂的非晶硅层上形成覆盖层。 形成一个联系人开放互连。 在互连表面上开口形成接触金属化，作为覆盖钛层，随后快速热退火以形成硅化物并汽提未反应的钛或通过在开口中选择性形成钨金属硅化物。 从设备剥去盖帽层。 在分裂硅层上形成第二非晶硅层。 重新结晶硅层以形成来自非晶硅层的多晶硅沟道层。 多晶硅沟道层的掺杂区域与栅电极上方的沟道区域不同。

公开(公告)号：US6093616A

公开(公告)日：2000-07-25

申请号：US75366

申请日：1998-05-11

申请人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chue-San Yoo

发明人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chue-San Yoo

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/40

摘要： This method forms a capacitor structure on a semiconductor substrate for providing split voltages for semiconductor circuits by the following steps. Form an active area in the substrate serving as a lower capacitor plate for a bottom capacitor and then form a thin dielectric layer and field oxide regions on the substrate, and cover the dielectric layer with a capacitor plate over the active area to complete the bottom capacitor. Form a thick dielectric layer over the device and a via through the thick dielectric layer to the upper capacitor plate. Form a second lower plate for a top capacitor. Form an inter-layer dielectric layer over the second lower plate. Form an upper capacitor layer over the inter-layer dielectric layer to form a top capacitor with a different capacitance value from the bottom capacitor. The value of the capacitance can be varied by selection of the permittivity and/or thickness of the dielectric layer and by variation of the effective plate area of the top and bottom capacitors.

摘要翻译： 该方法通过以下步骤在半导体基板上形成用于半导体电路的分压的电容器结构。 在用作底部电容器的下电容器板的衬底中形成有源区，然后在衬底上形成薄的电介质层和场氧化物区域，并且在有源区域上用电容器板覆盖电介质层以完成底部电容器 。 在器件上形成厚电介质层，并通过厚电介质层通孔到上电容器板。 形成顶部电容器的第二个下板。 在第二下板上形成层间电介质层。 在层间电介质层上形成上层电容层，形成与底层电容不同的电容值的顶层电容。 可以通过选择介电层的介电常数和/或厚度以及顶部和底部电容器的有效平板面积的变化来改变电容的值。

公开(公告)号：US6078087A

公开(公告)日：2000-06-20

申请号：US379230

申请日：1999-08-23

申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H07L27/11

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region. A doped interconnect line is also formed in the polysilicon conductive layer. There is a contact which extends through the gate oxide layer between the interconnection line and the polysilicon conductive layer.

摘要翻译： MOSFET SRAM器件中的导体和衬底区域之间的接触由部分完成的SRAM器件的表面上的介电层形成，该器件具有传输晶体管和锁存晶体管，其中介电层形成在那些通过和锁存晶体管之上。 在电介质层的上表面上形成薄膜晶体管栅电极和互连线。 栅极氧化层覆盖栅电极和互连线。 覆盖栅极氧化物层的多晶硅导电层包括形成在沟道区域的相对侧上的源极区域和漏极区域之间的沟道区域。 存在与形成在沟道区域上方的沟道区域以及栅极电极之上自对准的沟道掩模。 在沟道掩模之外掺杂多晶硅导电层，从而在沟道区的相对侧上提供源极区和漏极区。 掺杂的互连线也形成在多晶硅导电层中。 存在在互连线和多晶硅导电层之间延伸通过栅极氧化物层的接触。

公开(公告)号：US6054348A

公开(公告)日：2000-04-25

申请号：US79880

申请日：1998-05-15

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Mong-Song Liang

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Mong-Song Liang

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L29/66659

摘要： A process for creating a semiconductor memory device, featuring the formation of FOX regions, after the creation of a source region, has been developed. The process features a source region, self-aligned to a first set of stacked gate structures, with the subsequent FOX region placed perpendicular to the source region, between a second set of stacked gate structures.

摘要翻译： 已经开发了在创建源区域之后形成FOX区域的半导体存储器件的制造工艺。 该过程的特征在于源区域与第一组堆叠的栅极结构自对准，随后的FOX区域垂直于源区域放置在第二组堆叠栅极结构之间。

公开(公告)号：US5900658A

公开(公告)日：1999-05-04

申请号：US950233

申请日：1997-10-14

申请人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

发明人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L7/01

CPC分类号： H01L27/10844 ,  H01L21/823425 ,  H01L27/088

摘要： A semiconductor fabrication process has been developed in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic cell. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an underlying doped semiconductor regions.

摘要翻译： 已经开发了半导体制造工艺，其中DRAM和逻辑器件结构都集成在单个硅芯片上。 该过程的特征是组合了两种器件类型的工艺步骤，同时对于高容量DRAM单元以及CMOS逻辑单元仅使用单层多晶硅。 高容量DRAM单元由上覆多晶硅存储栅结构，薄介电层和下掺杂半导体区构成。

公开(公告)号：US5731232A

公开(公告)日：1998-03-24

申请号：US745639

申请日：1996-11-08

申请人： Shou-Gwo Wuu ,  Mong-Song Liang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/84 ,  Y10S257/903

摘要： A method is achieved for making TFT-load static random access memory (SRAM) cells where the thin film transistor (TFT) gate electrodes are made from an electrical conductor. At the same time, portions of the conductor between P and N doped polysilicon interconnections eliminate the P/N junction. Ohmic contacts are formed while avoiding additional processing steps. N-channel FET gate electrodes are formed from an N.sup.+ doped first polysilicon layer having a first insulating layer thereon. Second polySi interconnections are formed with a second insulating layer thereon. First contact openings are etched in the first and second insulating layers to the N.sup.+ doped FET gate electrodes, and a patterned conductor (TiN, TiSi.sub.2) forms the P-channel TFT gate electrodes and concurrently forms portions over and in the first contact openings. A TFT gate oxide is formed and second contact openings are etched over the first contact openings to the conductor. An N.sup.- doped third polySi layer is deposited, selectively doped P.sup.+ and patterned to form the TFT N.sup.- doped channel, the P.sup.+ doped source/drains, and the interconnection in the contact openings to the N-FET gate electrodes. The conductor at the interface between the P/N polySi forms essentially ohmic contacts, thereby eliminating the P/N junction and improving circuit performance.

摘要翻译： 实现了薄膜晶体管（TFT）栅电极由电导体制成的TFT负载静态随机存取存储器（SRAM）单元的方法。 同时，P和N掺杂多晶硅互连之间的导体部分消除了P / N结。 在避免额外的处理步骤的同时形成欧姆接触。 N沟道FET栅极由其上具有第一绝缘层的N +掺杂的第一多晶硅层形成。 第二多晶硅互连在其上形成有第二绝缘层。 第一接触开口在第一和第二绝缘层中蚀刻到N +掺杂FET栅电极，并且图案化导体（TiN，TiSi 2）形成P沟道TFT栅电极，同时在第一接触开口上并在其中形成部分。 形成TFT栅极氧化物，并且第二接触开口在第一接触开口上蚀刻到导体。 沉积N-掺杂的第三多晶硅层，选择性掺杂P +并图案化以形成TFT N掺杂沟道，P +掺杂源极/漏极以及在N-FET栅电极的接触开口中的互连。 在P / N多晶硅之间的界面处的导体形成基本的欧姆接触，从而消除P / N结并提高电路性能。

公开(公告)号：US5723374A

公开(公告)日：1998-03-03

申请号：US775049

申请日：1996-12-27

申请人： Julie Huang ,  Mong-Song Liang

发明人： Julie Huang ,  Mong-Song Liang

IPC分类号： H01L21/8242 ,  H01L23/532

CPC分类号： H01L27/10844 ,  H01L23/53223 ,  H01L2924/0002

摘要： A new method of avoiding the formation of a polysilicon stringer along the slope of the bit line contact hole edge is described. A gate electrode and associated source/drain regions are formed in and on the surface of a semiconductor substrate wherein the bit line contact is to be formed adjacent to the gate electrode. First spacers are formed on the sidewalls of the gate electrode. A first insulating layer over the gate electrode adjacent to the bit line contact has a first slope. Second spacers on the sidewalls of the first insulating layer adjacent to the bit line contact have a second slope less than the first slope. A second polysilicon layer is deposited overlying the gate electrode and patterned. A first dielectric layer and a third polysilicon layer is deposited overlying the second polysilicon layer. The third polysilicon layer is etched away where the bit line contact is to be formed. The gentler slope of the second spacers allows the third polysilicon layer to be etched away without leaving stringers. A bit line contact opening is etched through a second dielectric layer to the underlying semiconductor substrate wherein the bit line contact opening is separated from the third polysilicon layer by a thickness of the second dielectric layer. A fourth polysilicon layer is deposited within the contact opening to form the bit line contact.

摘要翻译： 描述了避免沿着位线接触孔边缘的斜面形成多晶硅桁条的新方法。 在半导体衬底的表面上和表面上形成栅电极和相关的源极/漏极区，其中位线接触将被形成为与栅电极相邻。 在栅电极的侧壁上形成第一间隔物。 与位线接触件相邻的栅电极上的第一绝缘层具有第一斜率。 与位线接触相邻的第一绝缘层的侧壁上的第二间隔物具有小于第一斜率的第二斜率。 第二多晶硅层沉积在栅电极上并被图案化。 覆盖在第二多晶硅层上的第一介电层和第三多晶硅层被沉积。 在要形成位线接触的位置蚀刻掉第三多晶硅层。 第二间隔物的温和倾斜允许第三多晶硅层被蚀刻掉而不留下桁条。 位线接触开口通过第二电介质层蚀刻到下面的半导体衬底，其中位线接触开口与第三多晶硅层分离第二电介质层的厚度。 在接触开口内沉积第四多晶硅层以形成位线接触。

公开(公告)号：US5719079A

公开(公告)日：1998-02-17

申请号：US654467

申请日：1996-05-28

申请人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

发明人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S148/019 ,  Y10S148/02

摘要： A method of forming a local interconnect in an SRAM, simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, is described. A semiconductor substrate on which MOS (Metal Oxide Semiconductor) transistors have been formed is provided. The transistors are separated by field isolation regions, and each transistor has a gate overlying a gate oxide and has source and drain regions in the substrate. Spacers are provided on the sidewalls of the gates, and some of the field oxide regions in the SRAM have polysilicon interconnects, with sidewall spacers. The sidewall spacers are removed from the polysilicon interconnects. A layer of titanium is deposited over the semiconductor substrate. A salicide is formed over the gates, the source and drain regions, and the polysilicon interconnects, so that the local interconnect is formed connecting the polysilicon interconnects to one of the source regions.

摘要翻译： 描述了在SRAM中形成局部互连的方法，同时在同一半导体衬底上的逻辑器件中形成硅化物。 提供其上形成有MOS（金属氧化物半导体）晶体管的半导体衬底。 晶体管由场隔离区域分离，并且每个晶体管具有覆盖栅极氧化物的栅极，并且在衬底中具有源极和漏极区域。 间隔件设置在栅极的侧壁上，SRAM中的一些场氧化物区域具有多晶硅互连，具有侧壁间隔物。 从多晶硅互连中去除侧壁间隔物。 在半导体衬底上沉积一层钛。 在栅极，源极和漏极区域以及多晶硅互连件之间形成自对准硅化物，使得局部互连形成为将多晶硅互连件连接到源极区域之一。