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    SRAM memory device with improved performance
    1.
    发明授权
    SRAM memory device with improved performance 有权
    TFT SRAM存储器件具有改进的性能

    公开(公告)号：US6078087A

    公开(公告)日：2000-06-20

    申请号：US379230

    申请日：1999-08-23

    申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

    发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H07L27/11

    CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region. A doped interconnect line is also formed in the polysilicon conductive layer. There is a contact which extends through the gate oxide layer between the interconnection line and the polysilicon conductive layer.

    摘要翻译： MOSFET SRAM器件中的导体和衬底区域之间的接触由部分完成的SRAM器件的表面上的介电层形成，该器件具有传输晶体管和锁存晶体管，其中介电层形成在那些通过和锁存晶体管之上。 在电介质层的上表面上形成薄膜晶体管栅电极和互连线。 栅极氧化层覆盖栅电极和互连线。 覆盖栅极氧化物层的多晶硅导电层包括形成在沟道区域的相对侧上的源极区域和漏极区域之间的沟道区域。 存在与形成在沟道区域上方的沟道区域以及栅极电极之上自对准的沟道掩模。 在沟道掩模之外掺杂多晶硅导电层，从而在沟道区的相对侧上提供源极区和漏极区。 掺杂的互连线也形成在多晶硅导电层中。 存在在互连线和多晶硅导电层之间延伸通过栅极氧化物层的接触。

    Method for manufacturing a TFT SRAM memory device with improved performance
    2.
    发明授权
    Method for manufacturing a TFT SRAM memory device with improved performance 失效
    制造具有改进性能的TFT SRAM存储器件的方法

    公开(公告)号：US5953606A

    公开(公告)日：1999-09-14

    申请号：US67151

    申请日：1998-02-27

    申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

    发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

    IPC分类号： H01L21/8244 ,  H01L27/11

    CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： A method of forming a contact between a conductor and a substrate region in a MOSFET SRAM starts with forming a dielectric layer on the surface of a partially completed SRAM device with pass and latch transistors covering the transistors. Then, form a thin film gate electrode and an interconnect on the dielectric layer with a gate oxide layer covering the gate electrode and the interconnect; cover the gate oxide layer with a poly conductive layer. Then form a silicon oxide layer over the poly conductive layer and pattern the silicon oxide layer to form a silicon oxide channel mask over the poly conductive layer which is used to pattern the silicon oxide layer into a channel mask over the gate electrode. The channel mask is used for patterning the implanting of dopant into the poly conductive layer aside from the channel mask to form a source region, a drain region and an interconnect in the poly conductive layer. Then form a contact through the gate oxide layer between the interconnect and the poly conductive layer by forming a tungsten layer over the poly conductive layer aside from the channel mask which remains in place.

    摘要翻译： 在MOSFET SRAM中形成导体和衬底区域之间的接触的方法开始于在部分完成的SRAM器件的表面上形成覆盖晶体管的通过和锁存晶体管的介质层。 然后，在电介质层上形成薄膜栅电极和互连，其中覆盖栅极和互连的栅氧化层; 用多导电层覆盖栅极氧化层。 然后在多导电层上形成氧化硅层，并对氧化硅层进行图案化以在多晶硅导电层上形成氧化硅沟道掩模，该导电层用于将氧化硅层图案化成栅电极上的沟道掩模。 沟道掩模用于图案化掺杂剂注入到沟道掩模之外的多导电层中以在多导电层中形成源极区域，漏极区域和互连。 然后通过在保持在适当位置的通道掩模之外的多导电层上形成钨层，通过互连和多导电层之间的栅极氧化层形成接触。

    Trench-free buried contact
    3.
    发明授权
    Trench-free buried contact 有权
    无沟槽埋地接触

    公开(公告)号：US06271570B1

    公开(公告)日：2001-08-07

    申请号：US09578414

    申请日：2000-05-26

    申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

    发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

    IPC分类号： H01L2976

    CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

    摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

    摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

    Method for forming a polysilicon-interconnect contact in a TFT-SRAM
    4.
    发明授权
    Method for forming a polysilicon-interconnect contact in a TFT-SRAM 失效
    在TFT-SRAM中形成多晶硅 - 互连触点的方法

    公开(公告)号：US6110822A

    公开(公告)日：2000-08-29

    申请号：US47539

    申请日：1998-03-25

    申请人： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

    发明人： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

    IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/44 ,  H01L21/00 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L27/11 ,  H01L21/76838 ,  H01L27/1108 ,  H01L21/2022

    摘要： A method of forming a contact in a thin film transistor with a gate electrode and an interconnect formed on a substrate, in an SRAM device comprises the following steps. Form a gate oxide layer over device. Form a split amorphous silicon layer over gate oxide layer. Form a cap layer over split amorphous silicon layer. Form a contact opening down to interconnect. Form contact metallization in opening on the surface of interconnect either as a blanket titanium layer followed by rapid thermal anneal to form a silicide and stripping unreacted titanium or by selective formation of a tungsten metal silicide in the opening. Strip cap layer from device. Form a second amorphous silicon layer on split silicon layer. Recrystallize silicon layers to form a polysilicon channel layer from amorphous silicon layers. Dope regions of polysilicon channel layer aside from a channel region above gate electrode.

    摘要翻译： 在SRAM器件中，在具有形成在衬底上的栅极和互连的薄膜晶体管中形成接触的方法包括以下步骤。 在器件上形成栅氧化层。 在栅极氧化层上形成分裂的非晶硅层。 在分裂的非晶硅层上形成覆盖层。 形成一个联系人开放互连。 在互连表面上开口形成接触金属化，作为覆盖钛层，随后快速热退火以形成硅化物并汽提未反应的钛或通过在开口中选择性形成钨金属硅化物。 从设备剥去盖帽层。 在分裂硅层上形成第二非晶硅层。 重新结晶硅层以形成来自非晶硅层的多晶硅沟道层。 多晶硅沟道层的掺杂区域与栅电极上方的沟道区域不同。

    Process to form a trench-free buried contact
    5.
    发明授权
    Process to form a trench-free buried contact 失效
    形成无沟槽埋层接触的工艺

    公开(公告)号：US6080647A

    公开(公告)日：2000-06-27

    申请号：US34927

    申请日：1998-03-05

    申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

    发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/3205

    CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

    摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

    摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

    Dishing-free gap-filling with multiple CMPs
    7.
    发明授权
    Dishing-free gap-filling with multiple CMPs 有权

    公开(公告)号：US08552522B2

    公开(公告)日：2013-10-08

    申请号：US13151666

    申请日：2011-06-02

    申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76883 ,  H01L21/76229

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

    Semiconductor device and method of fabricating same
    8.
    发明授权
    Semiconductor device and method of fabricating same 有权
    半导体装置及其制造方法

    公开(公告)号：US08461629B2

    公开(公告)日：2013-06-11

    申请号：US13178755

    申请日：2011-07-08

    申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

    摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

    摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。