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    Stacked package with electrical connections created using high throughput additive manufacturing
    92.
    发明授权
    Stacked package with electrical connections created using high throughput additive manufacturing 有权

    公开(公告)号：US11227859B2

    公开(公告)日：2022-01-18

    申请号：US16651331

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

    IPC: H01L25/10 ,  H01L21/48 ,  H01L23/367 ,  H01L25/00

    Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.

    Switched closed loop read-out methods and systems for resonant sensing platforms
    93.
    发明授权
    Switched closed loop read-out methods and systems for resonant sensing platforms 有权

    公开(公告)号：US11221354B2

    公开(公告)日：2022-01-11

    申请号：US15201144

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Georgios C. Dogiamis ,  Sasha N. Oster ,  Feras Eid ,  Ian A. Young

    IPC: G01R23/02 ,  G01D5/00 ,  H01L23/00 ,  G01D18/00 ,  G01P15/097

    Abstract: Embodiments of the invention include a resonant sensing system comprising driving circuitry to generate a drive signal during excitation time periods, a first switch coupled to the driving circuitry, and a sensing device coupled to the driving circuitry via the first switch during the excitation time periods. The sensing device includes beams to receive the drive signal during a first excitation time period that causes the beams to mechanically oscillate and generate a first induced electromotive force (emf) in response to the drive signal. The first switch decouples the sensing device and the driving circuitry during measurement time periods for measurement of the induced emf.

    INTEGRATED CIRCUIT DIE THERMAL SOLUTIONS WITH A CONTIGUOUSLY INTEGRATED HEAT PIPE
    94.
    发明申请
    INTEGRATED CIRCUIT DIE THERMAL SOLUTIONS WITH A CONTIGUOUSLY INTEGRATED HEAT PIPE 有权

    公开(公告)号：US20210410331A1

    公开(公告)日：2021-12-30

    申请号：US16911817

    申请日：2020-06-25

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Adel Elsherbini ,  Georgios Dogiamis

    IPC: H05K7/20 ,  H05K3/34

    Abstract: System-level thermal solutions for integrated circuit (IC) die packages including a heat pipe contiguously integrated with base plate material at the hot interface or with heat sink material at the cold interface. Base plate material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of the heat pipe to form a base plate suitable for interfacing with an IC die package. The contiguous base plate material may offer low thermal resistance in the absence of any intervening joining material (e.g., solder or brazing filler). Solder or brazing filler may also be eliminated from between a heat sink and a heat pipe by depositing wick material directly upon the heat sink with an HTAM technique. The wick material may be then enclosed by attaching a preformed half-open tube.

    ADDITIVELY MANUFACTURED STRUCTURES FOR HEAT DISSIPATION FROM INTEGRATED CIRCUIT DEVICES
    95.
    发明申请
    ADDITIVELY MANUFACTURED STRUCTURES FOR HEAT DISSIPATION FROM INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20210407884A1

    公开(公告)日：2021-12-30

    申请号：US16912432

    申请日：2020-06-25

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Xavier Brun ,  Paul Diglio ,  Joe Walczyk ,  Sergio Antonio Chan Arguedas

    IPC: H01L23/373 ,  B33Y80/00 ,  B33Y70/00

    Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

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