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公开(公告)号：US11073538B2
公开(公告)日：2021-07-27
申请号：US15861597
申请日：2018-01-03
申请人： Intel Corporation
发明人： Paul Diglio , Joe Walczyk
摘要： An electrical-test apparatus is provided, which includes a plurality of tester interconnect structures cantilevered from a first side of a substrate. A base may be coupled to a second side of the substrate via one or more interconnect layers. The tester interconnect structures may contact corresponding interconnect structures of a device under test (DUT). In an example, the substrate is laterally movable relative to the DUT along a plane of the substrate, upon contact between the tester interconnect structures and the interconnect structures of the DUT.
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公开(公告)号：US10935573B2
公开(公告)日：2021-03-02
申请号：US16145571
申请日：2018-09-28
申请人： Intel Corporation
发明人： Joe Walczyk , Pooya Tadayon
摘要： A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.
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公开(公告)号：US20180287305A1
公开(公告)日：2018-10-04
申请号：US15476582
申请日：2017-03-31
申请人： Intel Corporation
发明人： Youngseok Oh , Justin M. Huttula , Mohanraj Probhugoud , Ronald Kirby , Joe Walczyk , Erkan Acar
IPC分类号： H01R13/6594 , H01R13/11 , H01R13/6585 , H01R13/66 , H01R43/26
摘要： A shielded interconnect array and associated methods are described. Examples of the shielded interconnect array include socket connections that include conductive members with flexible bends. In examples shown, corresponding grounded conductive members with flexible bends are located adjacent to other conductive members with flexible bends to provide shielding.
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公开(公告)号：US09674943B2
公开(公告)日：2017-06-06
申请号：US13707032
申请日：2012-12-06
申请人： Intel Corporation
发明人： Youngseok Oh , Joe Walczyk
CPC分类号： H05K1/0268 , H01L2224/16225 , H01L2924/15311 , H05K1/116 , H05K3/4046
摘要： Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US20240203926A1
公开(公告)日：2024-06-20
申请号：US18593775
申请日：2024-03-01
申请人： Intel Corporation
IPC分类号： H01L23/00
CPC分类号： H01L24/29 , H01L2224/29287 , H01L2224/29293 , H01L2224/29324 , H01L2224/29339 , H01L2224/29347 , H01L2924/14 , H01L2924/351
摘要： An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.
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公开(公告)号：US12009612B2
公开(公告)日：2024-06-11
申请号：US17032587
申请日：2020-09-25
申请人： Intel Corporation
发明人： Srikant Nekkanty , Steven Klein , Feroz Mohammad , Joe Walczyk , Kuang Liu , Zhichao Zhang
CPC分类号： H01R13/11 , H05K1/0213 , H05K9/0022
摘要： Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.
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公开(公告)号：US20210407884A1
公开(公告)日：2021-12-30
申请号：US16912432
申请日：2020-06-25
申请人： Intel Corporation
IPC分类号： H01L23/373 , B33Y80/00 , B33Y70/00
摘要： An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.
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公开(公告)号：US10566263B2
公开(公告)日：2020-02-18
申请号：US15718337
申请日：2017-09-28
申请人： Intel Corporation
发明人： Joe Walczyk , John C. Johnson
IPC分类号： H01L23/427 , F28F1/40 , G01R31/26
摘要： A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing may define an interior chamber. The hollow housing may include a contact surface. The heat spreader may include a working fluid. The working fluid may be included in the interior chamber. The hollow housing may be configured to be physically compliant. The hollow housing may be physically compliant such that the hollow housing conforms to the shape of a testing surface in response to an applied pressure. The testing surface may be a top surface of a semiconductor. The testing surface may be curved or otherwise lack uniformity. The hollow housing may conform to the curvature or lack of uniformity of the testing surface such that minimal gaps exist between the hollow housing and the surface.
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公开(公告)号：US11948906B2
公开(公告)日：2024-04-02
申请号：US16785014
申请日：2020-02-07
申请人： INTEL CORPORATION
IPC分类号： H01L23/00
CPC分类号： H01L24/29 , H01L2224/29287 , H01L2224/29293 , H01L2224/29324 , H01L2224/29339 , H01L2224/29347 , H01L2924/14 , H01L2924/351
摘要： An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.
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公开(公告)号：US11372023B2
公开(公告)日：2022-06-28
申请号：US17174191
申请日：2021-02-11
申请人： Intel Corporation
发明人： Joe Walczyk , Pooya Tadayon
摘要： A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.
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