公开(公告)号：US20150206566A1

公开(公告)日：2015-07-23

申请号：US14159605

申请日：2014-01-21

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Xiaochen Guo ,  Hillery C. Hunter ,  Jude A. Rivers ,  Vijayalakshmi Srinivasan

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/04 ,  G11C11/1659 ,  G11C11/1693

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter , a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.

公开(公告)号：US20150162899A1

公开(公告)日：2015-06-11

申请号：US14623916

申请日：2015-02-17

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H02J1/00 ,  H02J1/14 ,  H03K3/0375 ,  H03K17/22 ,  H03K17/51 ,  Y10T307/469

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor.

公开(公告)号：US20150162898A1

公开(公告)日：2015-06-11

申请号：US14623847

申请日：2015-02-17

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H02J1/00 ,  H02J1/14 ,  H03K3/0375 ,  H03K17/22 ,  H03K17/51 ,  Y10T307/469

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor.

公开(公告)号：US20150134987A1

公开(公告)日：2015-05-14

申请号：US14603722

申请日：2015-01-23

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  Priyanka Tembey ,  Dilma Menezes Da Silva

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/50 ,  Y02D10/24

Abstract: Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

Abstract translation: 通过设置执行多线程应用程序的多核微处理器平台消耗的功耗的峰值功率级别来管理微处理器平台中的功耗。 多核微处理器平台包含多个物理核，每个物理核可配置成多个逻辑核。 响应于多核微处理器平台的功率消耗水平超过峰值功率水平，通过改变该物理核心上的逻辑核心数来调整至少一个物理核心中的同时多线程级别。 基于同步多线程级别的性能和功耗数据用于选择要调整的物理内核。

公开(公告)号：US20150082065A1

公开(公告)日：2015-03-19

申请号：US14171836

申请日：2014-02-04

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  Y02D10/171

Abstract: A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source.

Abstract translation: 为具有电源门控的集成电路提供了一种机制。 电源开关被配置为连接和断开电路到公共电压源。 电容器箱被配置为向给定的电路提供唤醒电荷。 可控元件连接到给定电路和电容器箱。 可控元件被配置为将电容器罐可控地连接和断开到给定电路，以便将唤醒电荷提供给给定电路。 可控元件被配置为响应于电源开关断开给定电路与公共电压源和给定电路被接通以唤醒，将唤醒电荷提供给给定的电路，该电路通过将唤醒电荷从 电容器槽给定电路。 这减少了从连接到公共电压源的电路传送的电荷。

公开(公告)号：US20150081125A1

公开(公告)日：2015-03-19

申请号：US14172052

申请日：2014-02-04

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: G05B13/02

CPC classification number: G06F1/3287 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/16 ,  Y02D10/171

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit.

公开(公告)号：US20150081123A1

公开(公告)日：2015-03-19

申请号：US14026494

申请日：2013-09-13

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: G05B13/02

CPC classification number: G06F1/3287 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/16 ,  Y02D10/171

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit.

Abstract translation: 为具有电源门控的集成电路提供了一种机制。 电源头开关被配置为将电路连接和断开到公共电压源。 电路断开时断路。 多路选择地将电荷泵或公共电压源连接到电源头开关的栅极端子。 电荷泵提供比公共电压源更高的电压到栅极端子。 控制器被配置为控制多路复用器对电荷泵和公共电压源的选择。 控制器被配置为将电荷泵与栅极端子断开，并将公共电压源连接到电源开关的栅极端子，以响应以下条件：预测需求核心上电请求，栅极泄漏增加 电流和/或断电电路的温度降低。

公开(公告)号：US20150077170A1

公开(公告)日：2015-03-19

申请号：US14026418

申请日：2013-09-13

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: H03K17/22

CPC classification number: H03K3/012 ,  H02J1/00 ,  H02J1/14 ,  H03K3/0375 ,  H03K17/22 ,  H03K17/51 ,  Y10T307/469

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor.

公开(公告)号：US20150076908A1

公开(公告)日：2015-03-19

申请号：US14171107

申请日：2014-02-03

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: H02J1/00

CPC classification number: H03K3/012 ,  H02J1/00 ,  H02J1/14 ,  H03K3/0375 ,  H03K17/22 ,  H03K17/51 ,  Y10T307/469

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor.

公开(公告)号：US20150074381A1

公开(公告)日：2015-03-12

申请号：US14019763

申请日：2013-09-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Xiaochen Guo ,  Hillery C. Hunter ,  Jude A. Rivers ,  Vijayalakshmi Srinivasan

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3808 ,  G06F9/3832

Abstract: A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.