公开(公告)号：US20220130714A1

公开(公告)日：2022-04-28

申请号：US17517247

申请日：2021-11-02

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522

Abstract: A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.

公开(公告)号：US11056390B2

公开(公告)日：2021-07-06

申请号：US16718820

申请日：2019-12-18

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US10892246B2

公开(公告)日：2021-01-12

申请号：US16740670

申请日：2020-01-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US10410977B2

公开(公告)日：2019-09-10

申请号：US15592973

申请日：2017-05-11

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01M2/08 ,  H01M2/16 ,  H01M2/18 ,  H01M4/02 ,  H01M4/04 ,  H01M4/52 ,  H01M4/80 ,  H01M4/485 ,  H05K1/00 ,  H05K3/10 ,  H05K3/40 ,  H05K3/46 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/02 ,  H05K1/03 ,  H01L23/15

Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.

公开(公告)号：US10396114B2

公开(公告)日：2019-08-27

申请号：US15407842

申请日：2017-01-17

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Michael Newman ,  Terrence Caskey

IPC: H01L23/49 ,  H01L27/146 ,  H05K1/02 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L21/683 ,  H01L23/00

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

公开(公告)号：US10325880B2

公开(公告)日：2019-06-18

申请号：US16197686

申请日：2018-11-21

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

公开(公告)号：US10297582B2

公开(公告)日：2019-05-21

申请号：US14952064

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Terrence Caskey ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Michael Newman ,  Pezhman Monadgemi ,  Reynaldo Co ,  Ellis Chau ,  Belgacem Haba

IPC: H01L25/10 ,  H05K1/02 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

公开(公告)号：US20190139878A1

公开(公告)日：2019-05-09

申请号：US16156595

申请日：2018-10-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/36 ,  H01L23/48 ,  H01L23/373 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76829 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/00 ,  H01L2924/0002

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

公开(公告)号：US10211160B2

公开(公告)日：2019-02-19

申请号：US15257152

申请日：2016-09-06

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Wael Zohni ,  Cyprian Emeka Uzoh

IPC: H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31

Abstract: A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.

公开(公告)号：US10163757B2

公开(公告)日：2018-12-25

申请号：US15452982

申请日：2017-03-08

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/768

Abstract: A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface.