公开(公告)号：US10957661B2

公开(公告)日：2021-03-23

申请号：US16528354

申请日：2019-07-31

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

公开(公告)号：US10700002B2

公开(公告)日：2020-06-30

申请号：US16446822

申请日：2019-06-20

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/14 ,  H01L21/48

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

公开(公告)号：US10586785B2

公开(公告)日：2020-03-10

申请号：US15927494

申请日：2018-03-21

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Liang Wang

IPC: H01L25/065 ,  H01L23/36 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L25/00

Abstract: A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

公开(公告)号：US10522457B2

公开(公告)日：2019-12-31

申请号：US16238786

申请日：2019-01-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/8234

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US10475733B2

公开(公告)日：2019-11-12

申请号：US16156595

申请日：2018-10-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/38 ,  H01L21/02 ,  H01L21/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L23/498 ,  H01L21/768 ,  H01L23/373 ,  H01L23/367 ,  H01L23/48 ,  H01L23/36

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

公开(公告)号：US10440822B2

公开(公告)日：2019-10-08

申请号：US15682049

申请日：2017-08-21

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K13/04 ,  H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/16 ,  H05K3/18

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US10418338B2

公开(公告)日：2019-09-17

申请号：US15830745

申请日：2017-12-04

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

公开(公告)号：US10283484B2

公开(公告)日：2019-05-07

申请号：US15164179

申请日：2016-05-25

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram

IPC: H05K3/07 ,  H01L23/00 ,  H01L21/683 ,  H01L23/367 ,  H01L23/373 ,  H01L25/065 ,  C25F3/12 ,  C25F3/14 ,  H05K1/02 ,  H05K1/11 ,  H01L21/48 ,  H01L23/498

Abstract: A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region.

公开(公告)号：US10177086B2

公开(公告)日：2019-01-08

申请号：US15952935

申请日：2018-04-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L21/8234

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20180366392A1

公开(公告)日：2018-12-20

申请号：US16037519

申请日：2018-07-17

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/49827 ,  H01L24/43 ,  H01L24/46 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/023 ,  H01L2224/4502 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.