公开(公告)号：US20060014314A1

公开(公告)日：2006-01-19

申请号：US11229655

申请日：2005-09-20

申请人： Dun-Nian Yaung ,  Chung-Yi Yu

发明人： Dun-Nian Yaung ,  Chung-Yi Yu

IPC分类号： H01L21/00

CPC分类号： H01L27/14685 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14625

摘要： An image sensor device and fabrication method thereof. An image sensing array is formed in a substrate, wherein the image sensing array comprises a plurality of photosensors with spaces therebetween. A first dielectric layer with a first refractive index is formed overlying the spaces but not the photosensors. A conformal second dielectric layer with a second refractive index is formed on a sidewall of the first dielectric layer. A third dielectric layer with a third refractive index is formed overlying the photosensors but not the spaces. The third refractive index is greater than the second refractive index. A light guide constructed by the second and third dielectric layers is formed overlying each photosensor, thereby preventing incident light from striking other photosensors.

摘要翻译： 一种图像传感器装置及其制造方法。 图像感测阵列形成在基板中，其中图像感测阵列包括在其间具有间隔的多个光电传感器。 具有第一折射率的第一介电层形成在空间上而不是光电传感器上。 在第一介电层的侧壁上形成具有第二折射率的共形的第二介电层。 形成具有第三折射率的第三介电层，覆盖光电传感器而不是空间。 第三折射率大于第二折射率。 由第二和第三电介质层构成的导光体形成在每个光电传感器上，从而防止入射光撞击其他感光体。

公开(公告)号：US20050164440A1

公开(公告)日：2005-07-28

申请号：US11084305

申请日：2005-03-18

申请人： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien

发明人： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L27/146 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/10897 ,  H01L27/14601 ,  H01L27/14609 ,  H01L27/14689 ,  H01L29/665

摘要： A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.

摘要翻译： 一种在半导体衬底上制造水化MOS和单面水化MOS器件的方法。 在第一和第二MOS器件和衬底上依次形成保形氧化物层和有机层。 第一MOS具有第一栅极结构，第一间隔物以及第一和第二掺杂区域。 第二MOS具有第二栅极结构，第二间隔物和第三和第四掺杂区域。 进行各向异性蚀刻以除去部分有机层，直到暴露出第一和第二栅极结构上的氧化物层，其中剩余的有机层留在衬底上。 去除第一和第二栅极结构上的氧化物层。 剩下的有机层被去除。 去除第一，第二和第三掺杂区域上的氧化物层。 因此，在第四掺杂区域上不能形成硅化物层。

公开(公告)号：US06897504B2

公开(公告)日：2005-05-24

申请号：US10403474

申请日：2003-03-31

申请人： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chen

发明人： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chen

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L27/146

CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/10897 ,  H01L27/14601 ,  H01L27/14609 ,  H01L27/14689 ,  H01L29/665

摘要： A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.

公开(公告)号：US20050062118A1

公开(公告)日：2005-03-24

申请号：US10669516

申请日：2003-09-24

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

IPC分类号： H01L21/00 ,  H01L21/82 ,  H01L27/14 ,  H01L27/146 ,  H01L29/82 ,  H01L31/00 ,  H04N5/335

CPC分类号： H01L31/103 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L31/02161

摘要： The present invention is a CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS image sensor with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless contact and dielectric structure covering the photodiode region. The dielectric structure is located between the photodiode and the interlevel dielectric (ILD) and is used as a buffer layer for the borderless contact. The method of fabricating a high performance photodiode comprises forming a photodiode in the n-well region of a shallow trench, and embedding a dielectric material between the ILD oxide and the photodiode having a refraction index higher than the ILD oxide.

摘要翻译： 本发明是CMOS图像传感器及其制造方法。 本发明提供了一种提高无边界接触CMOS图像传感器的量子效率的有效结构。 图像传感器包括覆盖光电二极管区域的无接触接触和介电结构的N阱/ P基板型光电二极管。 电介质结构位于光电二极管和层间电介质（ILD）之间，用作无边界接触的缓冲层。 制造高性能光电二极管的方法包括在浅沟槽的n阱区域中形成光电二极管，并且在ILD氧化物和具有高于ILD氧化物的折射率的光电二极管之间嵌入电介质材料。

公开(公告)号：US06852566B2

公开(公告)日：2005-02-08

申请号：US10386871

申请日：2003-03-12

申请人： Dun-Nian Yaung

发明人： Dun-Nian Yaung

IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L29/15 ,  H01L31/075 ,  H01L33/00

CPC分类号： H01L27/14687 ,  H01L27/14609 ,  H01L27/14643

摘要： A PIN active pixel sensor array including self aligned encapsulated electrodes and a method for forming the same the method including forming an electrically conductive layer over a substrate; forming a first doped semiconductor layer over the conductive layer; photolithographically patterning and etching through a thickness portion of the first doped semiconductor layer and conductive layer to expose the substrate to form a plurality of spaced apart electrodes having an upper portion comprising the first doped semiconductor layer; blanket depositing a second doped semiconductor layer to cover the spaced apart electrodes including the exposed substrate; and, etching through at least a thickness portion of the second doped semiconductor layer.

摘要翻译： 一种包括自对准密封电极的PIN有源像素传感器阵列及其形成方法，包括在衬底上形成导电层; 在所述导电层上形成第一掺杂半导体层; 光刻地图案化和蚀刻穿过第一掺杂半导体层和导电层的厚度部分以暴露衬底以形成多个间隔开的电极，其具有包括第一掺杂半导体层的上部; 覆盖沉积第二掺杂半导体层以覆盖包括暴露的衬底的间隔开的电极; 并且蚀刻通过至少第二掺杂半导体层的厚度部分。

公开(公告)号：US06806521B2

公开(公告)日：2004-10-19

申请号：US10338138

申请日：2003-01-08

申请人： Dun-Nian Yaung ,  Kuo-Ching Huang

发明人： Dun-Nian Yaung ,  Kuo-Ching Huang

IPC分类号： H01L31062

CPC分类号： H01L27/15 ,  H01L33/0004

摘要： A new method and structure for the combined creation of CMOS devices and LED devices. The process starts with a substrate over the surface of which are designated a first surface region for the creation of CMOS devices there-over and a second surface region for the creation of LED devices there-over. A relatively thick layer of gate oxide is created over the surface of the substrate. The first surface region is blocked by a mask of photoresist after which the second surface region is exposed to a plasma etch, thereby providing roughness to the surface of the relatively thick layer of gate oxide and reducing the thickness thereof. The blocking mask is removed, additional oxidation of the exposed surface creates a relatively thick layer of gate oxide over the first surface area and a relatively thin layer of gate oxide over the second surface area.

摘要翻译： 一种用于组合创建CMOS器件和LED器件的新方法和结构。 该过程从其表面上的衬底指定为用于在其上形成CMOS器件的第一表面区域和用于在其上形成LED器件的第二表面区域开始。 在衬底的表面上形成较厚的栅极氧化层。 第一表面区域被光致抗蚀剂掩模阻挡，之后第二表面区域暴露于等离子体蚀刻，从而为栅极氧化物的较厚层的表面提供粗糙度并减小其厚度。 去除阻挡掩模，暴露表面的额外氧化在第一表面区域上形成相对厚的栅极氧化物层，并在第二表面区域上形成相当薄的栅极氧化物层。

公开(公告)号：US06707080B2

公开(公告)日：2004-03-16

申请号：US10320296

申请日：2002-12-16

申请人： Ching-Chun Wang ,  Dun-Nian Yaung ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

发明人： Ching-Chun Wang ,  Dun-Nian Yaung ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC分类号： H01L31062

CPC分类号： H01L27/14645

摘要： A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.

摘要翻译： 实现了对CMOS彩色成像器上的红色，绿色和蓝色像素单元制造具有更均匀的光谱响应的光电二极管阵列的方法。 在衬底上形成场氧化物以电隔离CMOS电路的器件区域后，形成用于长波长红色像素单元的光电二极管的深N掺杂阱的阵列。 与N个掺杂的阱相邻并且与其交错形成P掺杂阱区的阵列。 在较短波长的绿色和蓝色像素单元的P掺杂阱内形成浅扩散的N +区。 浅扩散光电二极管提高了量子效率（QE），并提供了具有改进的色彩保真度的彩色成像仪。 在光电二极管上沉积并图案化绝缘层和适当的染料材料以提供彩色像素单元阵列。 N和P掺杂阱也用于支持FET CMOS电路以提供成本有效的制造工艺。

公开(公告)号：US06531752B2

公开(公告)日：2003-03-11

申请号：US09956219

申请日：2001-09-20

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chien-Hsien Tseng

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chien-Hsien Tseng

IPC分类号： H01L3106

CPC分类号： H01L31/103 ,  H01L27/14603 ,  H01L31/03529 ,  Y02E10/50

摘要： A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increased photon collection area, when compared to counterparts fabricated using non-serpentine shaped patterns. In addition the use of the serpentine shaped N type regions allow both vertical, as well as horizontal depletion regions, to result, thus increasing the quantum efficiency of the photodiode element. The combination of narrow width, and a reduced dopant level, for the N type serpentine shaped region, result in a fully depleted photodiode element.

公开(公告)号：US06518085B1

公开(公告)日：2003-02-11

申请号：US09635584

申请日：2000-08-09

申请人： Ching-Chun Wang ,  Dun-Nian Yaung ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

发明人： Ching-Chun Wang ,  Dun-Nian Yaung ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC分类号： H01L2100

CPC分类号： H01L27/14645

摘要： A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.

摘要翻译： 实现了对CMOS彩色成像器上的红色，绿色和蓝色像素单元制造具有更均匀的光谱响应的光电二极管阵列的方法。 在衬底上形成场氧化物以电隔离CMOS电路的器件区域后，形成用于长波长红色像素单元的光电二极管的深N掺杂阱的阵列。 与N个掺杂的阱相邻并且与其交错形成P掺杂阱区的阵列。 在较短波长的绿色和蓝色像素单元的P掺杂阱内形成浅扩散的N +区。 浅扩散光电二极管提高了量子效率（QE），并提供了具有改进的色彩保真度的彩色成像仪。 在光电二极管上沉积并图案化绝缘层和适当的染料材料以提供彩色像素单元阵列。 N和P掺杂阱也用于支持FET CMOS电路以提供成本有效的制造工艺。

公开(公告)号：US06372603B1

公开(公告)日：2002-04-16

申请号：US09612186

申请日：2000-07-07

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chien-Hsien Tseng

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chien-Hsien Tseng

IPC分类号： H01L2176

CPC分类号： H01L27/14689 ,  H01L21/76237 ,  H01L21/823878 ,  H01L27/14609

摘要： A method for forming a high performance photodiode with tightly-controlled junction profile for CMOS image sensor with STI process. The following steps are performed: providing a substrate; forming a hard mask layer for defining a pattern on the substrate; etching the substrate on the surface of the substrate not covered by the hard mask layer to form a shallow trench; growing an oxide lining in the shallow trench by a thermal oxidation process; performing a first thermal annealing; defining an n-well region in the shallow trench; implanting the n-well region; performing a second thermal annealing; forming a silicon oxide layer on the substrate to fill in the shallow trench; removing a portion of the silicon oxide layer on the substrate such that the portion in the shallow trench remains; removing the hard mask layer; and forming a transistor on the substrate, wherein the transistor comprises a gate structure, a source region, and a drain region.

摘要翻译： 一种用于具有STI工艺的CMOS图像传感器的具有紧密控制的结形状的高性能光电二极管的方法。 执行以下步骤：提供衬底; 形成用于在所述基板上限定图案的硬掩模层; 蚀刻未被硬掩模层覆盖的衬底的表面上的衬底，以形成浅沟槽; 通过热氧化过程在浅沟槽中生长氧化物衬里; 执行第一热退火; 在浅沟槽中限定n阱区域; 植入n阱区; 进行第二热退火; 在衬底上形成氧化硅层以填充浅沟槽; 去除衬底上的氧化硅层的一部分，使得浅沟槽中的部分保留; 去除硬掩模层; 以及在所述衬底上形成晶体管，其中所述晶体管包括栅极结构，源极区和漏极区。