公开(公告)号：US07847847B2

公开(公告)日：2010-12-07

申请号：US11044922

申请日：2005-01-27

Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/361 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

Abstract: A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

Abstract translation: 提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。 增加的电容可以降低噪声和暗信号。 图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。 附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。 本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

公开(公告)号：US5998269A

公开(公告)日：1999-12-07

申请号：US35139

申请日：1998-03-05

Applicant: Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

Inventor： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/3215 ,  H01L21/335 ,  H01L21/74

CPC classification number: H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US06806521B2

公开(公告)日：2004-10-19

申请号：US10338138

申请日：2003-01-08

Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang

Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang

IPC: H01L31062

CPC classification number: H01L27/15 ,  H01L33/0004

Abstract: A new method and structure for the combined creation of CMOS devices and LED devices. The process starts with a substrate over the surface of which are designated a first surface region for the creation of CMOS devices there-over and a second surface region for the creation of LED devices there-over. A relatively thick layer of gate oxide is created over the surface of the substrate. The first surface region is blocked by a mask of photoresist after which the second surface region is exposed to a plasma etch, thereby providing roughness to the surface of the relatively thick layer of gate oxide and reducing the thickness thereof. The blocking mask is removed, additional oxidation of the exposed surface creates a relatively thick layer of gate oxide over the first surface area and a relatively thin layer of gate oxide over the second surface area.

Abstract translation: 一种用于组合创建CMOS器件和LED器件的新方法和结构。 该过程从其表面上的衬底指定为用于在其上形成CMOS器件的第一表面区域和用于在其上形成LED器件的第二表面区域开始。 在衬底的表面上形成较厚的栅极氧化层。 第一表面区域被光致抗蚀剂掩模阻挡，之后第二表面区域暴露于等离子体蚀刻，从而为栅极氧化物的较厚层的表面提供粗糙度并减小其厚度。 去除阻挡掩模，暴露表面的额外氧化在第一表面区域上形成相对厚的栅极氧化物层，并在第二表面区域上形成相当薄的栅极氧化物层。

公开(公告)号：US20060164531A1

公开(公告)日：2006-07-27

申请号：US11044922

申请日：2005-01-27

Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

IPC: H04N5/335

CPC classification number: H04N5/361 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

Abstract: A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

Abstract translation: 提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。 增加的电容可以降低噪声和暗信号。 图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。 附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。 本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

公开(公告)号：US6110822A

公开(公告)日：2000-08-29

申请号：US47539

申请日：1998-03-25

Applicant: Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

Inventor： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

IPC: H01L21/20 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/44 ,  H01L21/00 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/11 ,  H01L21/76838 ,  H01L27/1108 ,  H01L21/2022

Abstract: A method of forming a contact in a thin film transistor with a gate electrode and an interconnect formed on a substrate, in an SRAM device comprises the following steps. Form a gate oxide layer over device. Form a split amorphous silicon layer over gate oxide layer. Form a cap layer over split amorphous silicon layer. Form a contact opening down to interconnect. Form contact metallization in opening on the surface of interconnect either as a blanket titanium layer followed by rapid thermal anneal to form a silicide and stripping unreacted titanium or by selective formation of a tungsten metal silicide in the opening. Strip cap layer from device. Form a second amorphous silicon layer on split silicon layer. Recrystallize silicon layers to form a polysilicon channel layer from amorphous silicon layers. Dope regions of polysilicon channel layer aside from a channel region above gate electrode.

Abstract translation: 在SRAM器件中，在具有形成在衬底上的栅极和互连的薄膜晶体管中形成接触的方法包括以下步骤。 在器件上形成栅氧化层。 在栅极氧化层上形成分裂的非晶硅层。 在分裂的非晶硅层上形成覆盖层。 形成一个联系人开放互连。 在互连表面上开口形成接触金属化，作为覆盖钛层，随后快速热退火以形成硅化物并汽提未反应的钛或通过在开口中选择性形成钨金属硅化物。 从设备剥去盖帽层。 在分裂硅层上形成第二非晶硅层。 重新结晶硅层以形成来自非晶硅层的多晶硅沟道层。 多晶硅沟道层的掺杂区域与栅电极上方的沟道区域不同。

公开(公告)号：US06351016B1

公开(公告)日：2002-02-26

申请号：US09389630

申请日：1999-09-03

Applicant: Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

Inventor： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC: H01L2976

CPC classification number: H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

Abstract: A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了埋地接触点。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US20080318454A1

公开(公告)日：2008-12-25

申请号：US11766204

申请日：2007-06-21

Applicant: Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

Inventor： Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

IPC: H01R12/16

CPC classification number: H05K1/0271 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit.

Abstract translation: 信息处理系统电路板具有通过其形成的开口，其靠近集成电路到电路板的耦合点。 开口处理集成电路到电路板的耦合点处的应力，以减少在电路板变形期间对耦合点的损坏的风险，例如当电路板耦合到底盘或当部件被按压时 进入电路板。 在一个实施例中，在BSA集成电路的对角相对的角上形成矩形开口。 在替代实施例中，在集成电路的选定角处形成变化形状的开口，例如槽或弯曲槽。

公开(公告)号：US20060061837A1

公开(公告)日：2006-03-23

申请号：US10904740

申请日：2004-11-24

Applicant: Kuo-Ching Huang ,  Yu-Cheng Chang

Inventor： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC: H04N1/23

CPC classification number: H04N1/1013 ,  H04N2201/0406 ,  H04N2201/0408 ,  H04N2201/0422

Abstract: A clamp for fixing a photographic slide and/or a photographic negative includes a carrier and a cover for fixing the slide or negative onto the carrier. The carrier includes a first guide for holding the negative, and a second guide extended from the first guide for holding the photographic slide.

Abstract translation: 用于固定照相底片和/或照相底片的夹具包括用于将滑块或阴极固定到载体上的载体和盖。 载体包括用于保持负片的第一引导件和从第一引导件延伸以保持照相载玻片的第二引导件。

公开(公告)号：US08853021B2

公开(公告)日：2014-10-07

申请号：US13273012

申请日：2011-10-13

Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

Abstract translation: 提供了一种用于电气设备的嵌入式晶体管，例如DRAM存储单元及其制造方法。 在衬底中形成沟槽，并且在衬底的沟槽中形成栅极电介质和栅电极。 源极/漏极区域形成在沟槽的相对侧上的衬底中。 在一个实施例中，源极/漏极区域中的一个耦合到存储节点，而另一个源极/漏极区域耦合到位线。 在该实施例中，栅电极可以耦合到字线以形成DRAM存储单元。

公开(公告)号：US08825122B2

公开(公告)日：2014-09-02

申请号：US13239359

申请日：2011-09-21

Applicant: Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

Inventor： Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

IPC: H05K7/00 ,  G06F1/16 ,  H05K5/02 ,  H04M1/02

CPC classification number: G06F1/1624 ,  H04M1/0237 ,  H04M1/0239

Abstract: A hand-held device includes a first body, a second body, a sliding module, and a guiding module. The sliding module is disposed between the first body and the second body, so that the second body is able to be slid on a two-dimensional plane relative to the first body. The guiding module includes a first guiding part and a second guiding part. The first guiding part is fixed to the first body. The second guiding part is fixed to the second body and coupled to the first guiding part. Besides, the second guiding part is able to be moved along a guiding path relative to the first guiding part, so that the second body is able to be slid along the guiding path on the two-dimensional plane relative to the first body.

Abstract translation: 手持式装置包括第一主体，第二主体，滑动模块和引导模块。 滑动模块设置在第一主体和第二主体之间，使得第二主体能够相对于第一主体在二维平面上滑动。 引导模块包括第一引导部分和第二引导部分。 第一个引导部分固定在第一个身体。 第二引导部分固定到第二主体并且联接到第一引导部分。 此外，第二引导部能够相对于第一引导部沿着引导路径移动，使得第二主体能够相对于第一主体沿着二维平面上的引导路径滑动。