公开(公告)号：US20050228612A1

公开(公告)日：2005-10-13

申请号：US10820292

申请日：2004-04-08

申请人： Jong-Hoon Oh

发明人： Jong-Hoon Oh

IPC分类号： G06F1/20 ,  G06F15/00 ,  G11C5/02 ,  G11C5/06

CPC分类号： G06F1/206

摘要： One embodiment of the present invention provides a multi-chip package including a logic device providing a clock signal having a frequency and a memory device. The memory device receives the clock signal and operates at the clock signal frequency. The memory device includes a temperature sensor providing a temperature signal indicative of a temperature of the memory device, wherein the logic device adjusts the clock signal frequency bases on the temperature signal.

摘要翻译： 本发明的一个实施例提供了一种包括提供具有频率的时钟信号的逻辑器件和存储器件的多芯片封装。 存储器件接收时钟信号并以时钟信号频率工作。 存储装置包括提供表示存储装置的温度的温度信号的温度传感器，其中逻辑装置根据温度信号调整时钟信号频率。

公开(公告)号：US20050207258A1

公开(公告)日：2005-09-22

申请号：US10805024

申请日：2004-03-18

申请人： Jong-Hoon Oh

发明人： Jong-Hoon Oh

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/842

摘要： One embodiment of the present invention provides a semiconductor memory receiving an external address including an array address and a row address. The semiconductor memory includes a memory bank having N arrays, each array having an array address and a plurality of primary rows of memory cells and a plurality of redundant rows of memory cells, a redundancy block, and N local row control blocks. The redundancy block provides a match signal having an active state when the external address matches one of a plurality of defective addresses, provides a redundant row address when the match signal has the active state, and provides a redirected array address comprising a redundant array address when the match signal has the active state and otherwise comprising the external array address. Each of the N local row control blocks is associated with a different one of the N arrays, wherein the local row control block associated with the array whose address matches the redirected array address opens a redundant row of memory cells for access based on the redundant row address when the match signal has the first state, and otherwise opens a normal row of memory cells for access based on the external row address.

摘要翻译： 本发明的一个实施例提供了接收包括阵列地址和行地址的外部地址的半导体存储器。 半导体存储器包括具有N个阵列的存储体，每个阵列具有阵列地址和存储器单元的多个主行和多个存储单元冗余行，冗余块和N个本地行控制块。 当外部地址匹配多个缺陷地址之一时，冗余块提供具有活动状态的匹配信号，当匹配信号具有活动状态时提供冗余行地址，并且当冗余阵列地址包括冗余阵列地址时 匹配信号具有活动状态，否则包括外部阵列地址。 N个本地行控制块中的每一个与N个阵列中的不同的一个相关联，其中与地址与重定向阵列地址匹配的阵列相关联的本地行控制块基于冗余行打开用于访问的冗余行存储器单元 匹配信号具有第一状态时的地址，否则基于外部行地址打开用于访问的正常的存储单元行。

公开(公告)号：US20050162957A1

公开(公告)日：2005-07-28

申请号：US10766428

申请日：2004-01-28

申请人： Jong-Hoon Oh

发明人： Jong-Hoon Oh

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/4076

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C2207/229

摘要： One embodiment of the present invention provides a random access memory including a command block and an array of memory cells. The command block is configured to provide a row signal having an active state in response to receiving a write command, wherein the active state occurs at a set time after receipt of the write command, and is configured to provide a write signal having at least a first active state, wherein the first active state of the write signal occurs at a set delay after the active state of the row signal. The array of memory cells is arranged in a plurality of rows and columns, wherein a selected row is opened for access in response to the active state of the row signal, and wherein data is written to at least one memory cell in the opened row in response to the at least first active state of the write signal.

摘要翻译： 本发明的一个实施例提供了包括命令块和存储器单元阵列的随机存取存储器。 所述命令块被配置为响应于接收到写入命令而提供具有活动状态的行信号，其中所述激活状态在接收到所述写命令之后的设定时间发生，并且被配置为提供具有至少一个 第一有效状态，其中写入信号的第一有效状态在行信号的有效状态之后以设定的延迟发生。 存储器单元的阵列被布置成多个行和列，其中响应于行信号的活动状态而打开所选择的行以进行访问，并且其中数据被写入打开的行中的至少一个存储单元 响应于写信号的至少第一活动状态。

公开(公告)号：US20050105367A1

公开(公告)日：2005-05-19

申请号：US10716749

申请日：2003-11-19

申请人： Jung Kim ,  Jong-Hoon Oh ,  Stephen Bowyer ,  George Alexander

发明人： Jung Kim ,  Jong-Hoon Oh ,  Stephen Bowyer ,  George Alexander

IPC分类号： G11C5/14 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00 ,  G11C5/00

CPC分类号： G11C11/40626 ,  G11C5/14 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4068

摘要： Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The device temperature may be measured directly, for example, via an on-chip temperature sensor, or may be supplied as bits in a mode register containing temperature information.

摘要翻译： 提供了用于基于存储器件的温度改变存储器件的一个或多个内部产生的电压的方法和装置。 器件温度可以直接例如通过片上温度传感器测量，或者可以作为包含温度信息的模式寄存器中的位来提供。

公开(公告)号：US06606272B2

公开(公告)日：2003-08-12

申请号：US09823325

申请日：2001-03-29

申请人： Jong-Hoon Oh ,  Young-Seog Kim

发明人： Jong-Hoon Oh ,  Young-Seog Kim

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C7/1039 ,  G11C7/1051

摘要： A circuit according to the present invention includes a plurality of data registers each coupled between the output terminal and a data bus. Each data register stores successive data bits received serially from the data bus. The circuit also includes a plurality of output enable signals each coupled to a corresponding data register. Additionally, the circuit includes a mode select circuit to program the plurality of output enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width greater than the first pulse width. The circuit may be included as part of a memory circuit in a memory system.

公开(公告)号：US06011746A

公开(公告)日：2000-01-04

申请号：US182943

申请日：1998-10-29

申请人： Jong-Hoon Oh

发明人： Jong-Hoon Oh

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C8/14 ,  G11C11/4085 ,  G11C8/08

摘要： A hierarchical word line driving structure uses a shared inverter circuit architecture which allows for lower power consumption and a pulsed control signal to ensure accurate memory retrieval. The shared inverter word line structure includes a row decoder, a first sub-word line driver, a second sub-word line driver, and an interconnect line. The first sub-word line driver includes an inverting circuit for inverting the signal propagating along the global word line, while the second sub-word line driver does not. The interconnect line is coupled between the first and second sub-word line drivers to communicate the inverted signal therebetween. A pulsed control signal is supplied to clamping transistors connected to unselected word lines to ensure they remain clamped to ground.

摘要翻译： 分级字线驱动结构使用共享的逆变器电路架构，其允许较低的功耗和脉冲控制信号以确保准确的存储器检索。 共享的逆变器字线结构包括行解码器，第一子字线驱动器，第二子字线驱动器和互连线。 第一子字线驱动器包括用于反转沿着全局字线传播的信号的反相电路，而第二子字线驱动器不反相。 互连线耦合在第一和第二子字线驱动器之间以在其间传送反相信号。 脉冲控制信号被提供给连接到未选字线的钳位晶体管，以确保它们保持钳位到地。