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公开(公告)号：US11538860B2
公开(公告)日：2022-12-27
申请号：US17130215
申请日：2020-12-22
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Lorenzo Fratin , Hongmei Wang
IPC: H01L27/24 , H01L45/00 , H01L23/528 , H01L21/66 , H01L23/532
Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.
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公开(公告)号：US11538513B2
公开(公告)日：2022-12-27
申请号：US16542975
申请日：2019-08-16
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Fabio Pellizzer
Abstract: An output, representing synaptic weights of a neural network can be received from first memory elements. The output can be compared to a known correct output. A random number can be generated with a tuned bias via second memory elements. The weights can be updated based on the random number and a difference between the output and the known correct output.
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公开(公告)号：US11514983B2
公开(公告)日：2022-11-29
申请号：US17221417
申请日：2021-04-02
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Fabio Pellizzer , Nevil N. Gajera
Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.
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公开(公告)号：US20220343978A1
公开(公告)日：2022-10-27
申请号：US17238056
申请日：2021-04-22
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer
IPC: G11C13/00
Abstract: Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.
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公开(公告)号：US11482284B1
公开(公告)日：2022-10-25
申请号：US17238056
申请日：2021-04-22
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer
Abstract: Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.
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Patent Agency Ranking
公开(公告)号：US20220319587A1
公开(公告)日：2022-10-06
申请号：US17221417
申请日：2021-04-02
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Fabio Pellizzer , Nevil N. Gajera
Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.
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公开(公告)号：US20220190031A1
公开(公告)日：2022-06-16
申请号：US17119038
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.
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公开(公告)号：US20220189549A1
公开(公告)日：2022-06-16
申请号：US17118844
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Paolo Fantini , Fabio Pellizzer , Thomas M. Graettinger
IPC: G11C13/00
Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.
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公开(公告)号：US20220189548A1
公开(公告)日：2022-06-16
申请号：US17117953
申请日：2020-12-10
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Lorenzo Fratin , Fabio Pellizzer
Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.
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公开(公告)号：US11342382B1
公开(公告)日：2022-05-24
申请号：US17119038
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.
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