公开(公告)号：US5679585A

公开(公告)日：1997-10-21

申请号：US746774

申请日：1996-11-15

申请人： Mark I. Gardner ,  Fred N. Hause ,  Derick J. Wristers ,  Dim-Lee Kwong

发明人： Mark I. Gardner ,  Fred N. Hause ,  Derick J. Wristers ,  Dim-Lee Kwong

IPC分类号： H01L21/285 ,  H01L21/283

CPC分类号： H01L21/28518 ,  Y10S438/909

摘要： An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and especially in small silicide formation areas. The higher pressure helps ensure thermal contact of heated, flowing gas across relatively small geometries in which silicide is to be formed. Substantial metal silicide formation can occur at the higher pressures even under relatively lower temperature conditions. The lower temperature process helps ensure that pre-existing implant regions remain at their initial position. The present metal silicide process and lower temperature anneal is therefore well suited to avoid impurity migration problems such as, for example, threshold skew, parasitic junction capacitance enhancement, and gate oxide degradation.

摘要翻译： 提供了一种在半导体形貌上制造金属硅化物的方法。 该方法有利地在基本上较低的温度下进行退火循环。 通过采用高压退火室，在半导体形貌特别是在小的硅化物形成区域中实现了温度平衡。 较高的压力有助于确保加热的流动气体在要形成硅化物的较小几何形状上的热接触。 即使在相对较低的温度条件下，也可能在更高的压力下发生大量金属硅化物的形成。 较低的温度过程有助于确保预先存在的植入区域保持在其初始位置。 因此，目前的金属硅化物工艺和较低温度退火非常适合于避免杂质迁移问题，例如阈值偏移，寄生结电容增强和栅极氧化物降解。

公开(公告)号：US5672531A

公开(公告)日：1997-09-30

申请号：US682493

申请日：1996-07-17

申请人： Mark I. Gardner ,  Michael P. Duane ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Michael P. Duane ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/265 ,  H01L21/44

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： A method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, the method includes providing a semiconductor substrate having a gate insulator and a gate electrode, the gate electrode having opposing first and second sidewalls defining the length of the gate electrode and a top surface. Lightly doped source and drain regions are implanted into the semiconductor substrate and are substantially aligned with the sidewalls of the gate electrode. After implanting the lightly doped regions, first and second spacers are formed adjacent to the first and second sidewalls of the gate electrode. After forming the spacers, a portion of the gate electrode is removed to form a third sidewall of the gate electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the gate electrode. After removing the first spacer, heavily doped source and drain regions are implanted into the semiconductor substrate. The heavily doped drain region is substantially aligned with the outer edge of the second spacer, a portion of the lightly doped drain region is protected beneath the second spacer, and the heavily doped source region is substantially aligned with the third sidewall. In another embodiment, the heavily doped drain region is implanted after the spacers are formed but before the third sidewall is formed and the heavily doped source region is implanted after forming the third sidewall.

摘要翻译： 描述了一种用于制造非对称LDD-IGFET的方法。 在一个实施例中，该方法包括提供具有栅极绝缘体和栅电极的半导体衬底，所述栅电极具有限定栅电极的长度和顶表面的相对的第一和第二侧壁。 将轻掺杂的源极和漏极区域注入到半导体衬底中并且基本上与栅电极的侧壁对准。 在注入轻掺杂区域之后，在栅电极的第一和第二侧壁附近形成第一和第二间隔物。 在形成间隔物之后，去除栅电极的一部分以形成与第二侧壁相对的栅电极的第三侧壁，从而消除第一侧壁并减小栅电极的长度。 在去除第一间隔物之后，将重掺杂的源极和漏极区域注入到半导体衬底中。 重掺杂漏极区域基本上与第二间隔物的外边缘对准，轻掺杂漏极区域的一部分被保护在第二间隔物下方，并且重掺杂源极区域基本上与第三侧壁对准。 在另一个实施例中，在形成间隔物之后但在形成第三侧壁之前注入重掺杂漏极区，并且在形成第三侧壁之后注入重掺杂源极区。

公开(公告)号：US06531364B1

公开(公告)日：2003-03-11

申请号：US09129703

申请日：1998-08-05

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

摘要： A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.

摘要翻译： 提出了一种用于形成晶体管的方法，其中多晶硅优选沉积在介电覆盖的衬底上以形成牺牲多晶硅层。 然后可以将牺牲多晶硅层还原成所需的厚度。 牺牲多晶硅层的厚度减少优选通过氧化牺牲多晶硅层的一部分然后蚀刻氧化部分进行。 作为选择，可以加热牺牲多晶硅层使其重结晶。 牺牲多晶硅层优选在含氮环境中退火，使得其被转换成包括氮化物的栅极电介质层。 多晶硅可以沉积在栅极介电层上，并且可以去除多晶硅的部分以形成栅极导体。 LDD和源极/漏极区域可以形成在栅极导体附近。

公开(公告)号：US06303962B1

公开(公告)日：2001-10-16

申请号：US09227512

申请日：1999-01-06

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

IPC分类号： A01L2701

CPC分类号： H01L29/66757 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/78675

摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operation speed.

摘要翻译： 在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。 晶体管的栅极也可以由诸如金属的低电阻材料形成。 晶体管沟道位于布置在半导体衬底上的电介质层上的多晶硅层中。 为了制造晶体管，在半导体衬底上沉积隔离电介质，多晶硅层和保护电介质层。 源极/漏极沟槽形成在保护电介质层和多晶硅层中，随后填充有牺牲电介质。 位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。 随后去除牺牲电介质并用可由低电阻金属形成的源极/漏极区域代替。 所得到的晶体管可以表现出低接触和串联电阻，并且增加了操作速度。

公开(公告)号：US06255698B1

公开(公告)日：2001-07-03

申请号：US09301263

申请日：1999-04-28

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr.

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).

摘要翻译： 提供并形成了包含用于n沟道和p沟道晶体管的单独优化的栅极结构的集成电路。 用于n沟道和p沟道晶体管的原始栅极结构在半导体衬底的适当掺杂的有源区上被图案化。 在半导体衬底上形成与原始栅极结构的上表面相同的高度水平面的保护电介质，使得只有栅极结构的上表面露出。 掩模层用于覆盖p沟道或n沟道晶体管的栅极结构。 去除未覆盖的栅极结构，在保护电介质内形成沟槽，代替每个去除的栅极结构。 沟槽用新的栅极结构重新填充，该栅极结构优选地适合于适当的晶体管类型（n沟道或p沟道）的操作。

公开(公告)号：US06239467B1

公开(公告)日：2001-05-29

申请号：US09183616

申请日：1998-10-30

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Anthony Toprac

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Anthony Toprac

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L22/20 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/90 ,  H01L2924/00

摘要： A semiconductor device having a controlled drive current strength is produced by varying spacer width to accommodate any variation in gate electrode length from a desired value. After formation of the gate electrode on a substrate, the length is measured and compared to a desired value. Based on any differences between the measured and desired values, the width of spacer is determined in order to counteract the variation in gate electrode length. This results in maintaining the desired channel length after dopant implanting, to provide the desired drive current strength. The present process permits close control over the drive current strength of semiconductor devices and also decreased variation within and between lots and corresponding increases in productivity.

摘要翻译： 具有受控的驱动电流强度的半导体器件通过改变间隔物宽度来产生，以适应栅电极长度与期望值的任何变化。 在基板上形成栅电极之后，测量长度并将其与期望值进行比较。 基于测量值和期望值之间的任何差异，确定间隔物的宽度以抵消栅电极长度的变化。 这导致在掺杂剂注入之后保持期望的沟道长度，以提供期望的驱动电流强度。 本方法允许对半导体器件的驱动电流强度进行密切控制，并且还可以减少批次之间和批量之间的变化，并且相应地提高生产率。

公开(公告)号：US06225646B1

公开(公告)日：2001-05-01

申请号：US09483557

申请日：2000-01-14

申请人： Mark I. Gardner ,  H. Jim Fulford

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L3300

CPC分类号： H01L27/0688 ,  H01L21/84 ,  H01L27/1203

摘要： An integrated circuit is presented. The integrated circuit may include a memory cell formed above an insulating base. The insulating base may either be arranged above a substrate or serve as a substrate itself. A transistor may be arranged above the memory cell. The transistor is preferably dielectrically isolated from the memory cell. In a preferred embodiment, a segmented substrate is arranged between the memory cell and transistor. The segmented substrate preferably includes a first conductive substrate layer arranged above and dielectrically spaced from the memory cell. A second conductive substrate layer may be formed above the first conductive substrate layer. The transistor may be arranged upon and within the second conductive substrate layer. Preferably, the segmented substrate further includes an intersubstrate dielectric layer interposed between the second conductive substrate layer and the first conductive substrate layer. The intersubstrate dielectric layer preferably serves to insulate the first conductive substrate layer from the second conductive substrate layer. An integrated circuit so configured may be fabricated with greater device density at reduced cost.

摘要翻译： 介绍了一个集成电路。 集成电路可以包括形成在绝缘基底上方的存储单元。 绝缘基底可以布置在基底之上或用作基底本身。 晶体管可以布置在存储器单元的上方。 晶体管优选地与存储单元介电隔离。 在优选实施例中，分段衬底被布置在存储器单元和晶体管之间。 分段基板优选​​地包括布置在存储单元上方并与该存储单元间隔开的第一导电基板层。 第二导电衬底层可以形成在第一导电衬底层的上方。 晶体管可以布置在第二导电衬底层之上和之内。 优选地，分段基板还包括插入在第二导电基板层和第一导电基板层之间的基板间电介质层。 衬底间电介质层优选用于使第一导电衬底层与第二导电衬底层绝缘。 如此构造的集成电路可以以更低的成本制造具有更大的器件密度。

公开(公告)号：US06207520B1

公开(公告)日：2001-03-27

申请号：US08993918

申请日：1997-12-18

申请人： Mark I. Gardner ,  H. Jim Fulford

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2251 ,  H01L21/2652 ,  H01L21/823807

摘要： Rapid thermal anneal with a gaseous dopant species for formation of a shallow lightly doped region is disclosed. In one embodiment of the invention, a method includes four steps. In the first step, at least one layer is applied over at least one gate over a semiconductor substrate. In the second step, an ion implantation is performed to form source and drain regions within the substrate. In the third step, the layers are removed. In the fourth step, a rapid thermal anneal with a gaseous dopant species is performed to form lightly doped regions within the substrate.

摘要翻译： 公开了用于形成浅轻掺杂区域的气态掺杂物种的快速热退火。 在本发明的一个实施例中，一种方法包括四个步骤。 在第一步骤中，在半导体衬底上的至少一个栅极上施加至少一层。 在第二步骤中，进行离子注入以在衬底内形成源区和漏区。 在第三步中，层被去除。 在第四步骤中，进行与气态掺杂剂物质的快速热退火以在衬底内形成轻掺杂区域。

公开(公告)号：US06169006A

公开(公告)日：2001-01-02

申请号：US09124604

申请日：1998-07-29

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L29/4983

摘要： A semiconductor device having grown oxide spacers and a method for manufacturing such a semiconductor device is provided. In one embodiment of the invention, a gate electrode is formed over a substrate, and an oxidation-resistant layer is formed adjacent to the gate electrode. The gate electrode is oxidized to grow an oxide layer on the gate electrode extending over the oxidation-resistant layer. One or more spacers then is formed adjacent to the gate electrode using the oxide layer.

摘要翻译： 提供了具有生长的氧化物间隔物的半导体器件和制造这种半导体器件的方法。 在本发明的一个实施例中，栅极电极形成在衬底上，并且与栅电极相邻形成抗氧化层。 氧化栅极以在氧化层上延伸的栅电极上生长氧化物层。 然后使用氧化物层在栅电极附近形成一个或多个间隔物。

公开(公告)号：US06168958A

公开(公告)日：2001-01-02

申请号：US09130494

申请日：1998-08-07

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L2976

CPC分类号： H01L27/088 ,  H01L21/823462

摘要： A semiconductor structure having multiple thicknesses of high-k gate dielectrics and a process of manufacture. In one embodiment, semiconductor structure is provided that includes a substrate, and a high permittivity layer is disposed on the substrate, the high permittivity layer having two or more areas with different thicknesses. A plurality of gate electrodes are disposed in the two or more areas on the high permittivity layer. In another embodiment, a process for constructing a semiconductor structure includes depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness. A first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness. Selected portions of the high permittivity layer are then removed, whereby the high permittivity layer is reduced to a second thickness. Then a second set of gate electrodes are formed on the selected portions of the high permittivity layer having the second thickness.

摘要翻译： 具有多个厚度的高k栅极电介质的半导体结构和制造工艺。 在一个实施例中，提供了包括衬底的半导体结构，并且高介电常数层设置在衬底上，高电容率层具有两个或更多个具有不同厚度的区域。 多个栅电极设置在高电容率层上的两个或更多个区域中。 在另一个实施例中，用于构造半导体结构的工艺包括在衬底上沉积高介电常数层，高介电常数层具有第一厚度。 在具有第一厚度的高电容率层上形成第一组一个或多个栅电极。 然后去除高介电常数层的选定部分，由此将高介电常数层减小到第二厚度。 然后，在具有第二厚度的高介电常数层的选定部分上形成第二组栅电极。