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公开(公告)号：US5672531A
公开(公告)日：1997-09-30
申请号：US682493
申请日：1996-07-17
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265 , H01L21/44
CPC分类号： H01L29/66659 , H01L29/7835
摘要： A method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, the method includes providing a semiconductor substrate having a gate insulator and a gate electrode, the gate electrode having opposing first and second sidewalls defining the length of the gate electrode and a top surface. Lightly doped source and drain regions are implanted into the semiconductor substrate and are substantially aligned with the sidewalls of the gate electrode. After implanting the lightly doped regions, first and second spacers are formed adjacent to the first and second sidewalls of the gate electrode. After forming the spacers, a portion of the gate electrode is removed to form a third sidewall of the gate electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the gate electrode. After removing the first spacer, heavily doped source and drain regions are implanted into the semiconductor substrate. The heavily doped drain region is substantially aligned with the outer edge of the second spacer, a portion of the lightly doped drain region is protected beneath the second spacer, and the heavily doped source region is substantially aligned with the third sidewall. In another embodiment, the heavily doped drain region is implanted after the spacers are formed but before the third sidewall is formed and the heavily doped source region is implanted after forming the third sidewall.
摘要翻译： 描述了一种用于制造非对称LDD-IGFET的方法。 在一个实施例中，该方法包括提供具有栅极绝缘体和栅电极的半导体衬底，所述栅电极具有限定栅电极的长度和顶表面的相对的第一和第二侧壁。 将轻掺杂的源极和漏极区域注入到半导体衬底中并且基本上与栅电极的侧壁对准。 在注入轻掺杂区域之后，在栅电极的第一和第二侧壁附近形成第一和第二间隔物。 在形成间隔物之后，去除栅电极的一部分以形成与第二侧壁相对的栅电极的第三侧壁，从而消除第一侧壁并减小栅电极的长度。 在去除第一间隔物之后，将重掺杂的源极和漏极区域注入到半导体衬底中。 重掺杂漏极区域基本上与第二间隔物的外边缘对准，轻掺杂漏极区域的一部分被保护在第二间隔物下方，并且重掺杂源极区域基本上与第三侧壁对准。 在另一个实施例中，在形成间隔物之后但在形成第三侧壁之前注入重掺杂漏极区，并且在形成第三侧壁之后注入重掺杂源极区。
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2.发明授权公开(公告)号：US06979878B1
公开(公告)日：2005-12-27
申请号：US09217213
申请日：1998-12-21
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
摘要翻译： 一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。 该方法包括在半导体衬底上形成电介质掩模层。 然后通过掩模层形成开口。 在开口内的掩模层的侧壁上形成一对电介质隔离物。 然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。 然后在沟槽的壁和基底上热生长第一介电层。 将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。 间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。 然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。
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3.发明授权CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof 有权CMOS集成电路和用于在注入PMOS晶体管区域之前注入NMOS晶体管区域以优化其热扩散率的方法公开(公告)号：US06258646B1
公开(公告)日：2001-07-10
申请号：US09149631
申请日：1998-09-08
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , Y10S257/90
摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.
摘要翻译： 提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。 首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。 首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。 与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。 通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。
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4.发明授权Method of forming an insulated-gate field-effect transistor with metal spacers 有权用金属间隔物形成绝缘栅场效应晶体管的方法公开(公告)号：US06188114B1
公开(公告)日：2001-02-13
申请号：US09204016
申请日：1998-12-01
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31119
CPC分类号： H01L29/41783 , H01L29/41775 , H01L29/66575 , H01L29/6659
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。
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5.发明授权High performance transistor fabricated on a dielectric film and method of making same 有权在介电膜上制造的高性能晶体管及其制造方法公开(公告)号：US06188107B1
公开(公告)日：2001-02-13
申请号：US09226564
申请日：1999-01-07
IPC分类号： H01L2900
CPC分类号： H01L29/78696 , H01L29/66757 , H01L29/78636
摘要： The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said layer of dielectric material and between said source/drain regions. The method further comprises forming a gate dielectric above said layer of polysilicon and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a layer of dielectric material, a plurality of source/drain regions positioned above the layer of dielectric material, and a layer of polysilicon positioned above said layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above said layer of polysilicon and a gate conductor positioned above said gate dielectric.
摘要翻译： 本发明涉及一种形成在电介质材料层上方的晶体管及其制造方法。 在一个说明性实施例中，所述方法包括形成介电材料层，在所述源极/漏极区之间形成由多晶硅上方的多个源极/漏极区域组成的电介质材料层。 该方法还包括在所述多晶硅层上形成栅极电介质，并在所述栅极电介质上方形成栅极导体。 晶体管结构由介电材料层，位于介电材料层之上的多个源极/漏极区域和位于介电材料层上方之间以及所述源极/漏极区域之间的多晶硅层构成。 该结构还包括位于所述多晶硅层上方的栅极电介质和位于所述栅极电介质上方的栅极导体。
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6.发明授权System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication 失效用于半导体制造中退火的原位监测和控制的系统和装置
公开(公告)号：US6166354A
公开(公告)日：2000-12-26
申请号：US876381
申请日：1997-06-16
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.
摘要翻译： 在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。 在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。 监测表面光电压测量，检测退火时间，并控制所选择的过退火。 执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。 在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。 检测点也用于终止退火过程以最小化Dt。
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7.发明授权Method of fabricating a transistor with a dielectric underlayer and device incorporating same 有权制造具有电介质底层的晶体管的方法和结合其的器件
公开(公告)号：US6162688A
公开(公告)日：2000-12-19
申请号：US231427
申请日：1999-01-14
IPC分类号： H01L21/266 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/06 , H01L29/49 , H01L29/51 , H01L29/786 , H01L21/00
CPC分类号： H01L21/28194 , H01L21/266 , H01L21/268 , H01L21/28158 , H01L21/28202 , H01L21/823842 , H01L27/0688 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545 , H01L29/66757 , H01L29/78636
摘要： A method is provided for fabricating a transistor, the method including forming a dielectric layer above a structure, forming a first polysilicon layer above the dielectric layer and forming a sacrificial region above the first polysilicon layer. The method also includes forming a second polysilicon layer above the first polysilicon layer and adjacent the sacrificial region. The method further includes removing the sacrificial region to form an opening in the second polysilicon layer, the opening having sidewalls, and forming dielectric spacers on the sidewalls of the opening. In addition, the method includes forming a gate dielectric within the opening above the first polysilicon layer and forming a gate conductor above the gate dielectric.
摘要翻译： 提供了一种用于制造晶体管的方法，所述方法包括在结构之上形成电介质层，在电介质层上方形成第一多晶硅层，并在第一多晶硅层上方形成牺牲区域。 该方法还包括在第一多晶硅层上形成第二多晶硅层并且邻近牺牲区。 该方法还包括去除牺牲区域以在第二多晶硅层中形成开口，该开口具有侧壁，并在开口的侧壁上形成电介质间隔物。 此外，该方法包括在第一多晶硅层上方的开口内形成栅极电介质，并在栅极电介质上方形成栅极导体。
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8.发明授权Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance 失效集成电路具有耦合到具有源极/漏极区域的源极/漏极区域的层间互连重叠和减小的寄生电容
公开(公告)号：US6146978A
公开(公告)日：2000-11-14
申请号：US73639
申请日：1998-05-06
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/8238 , H01L21/44 , H01L21/4763 , H01L31/119
CPC分类号： H01L21/823871 , H01L21/76802 , H01L21/76895
摘要： An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.
摘要翻译： 在通过隔离层打开的窗口中并通过蚀刻屏障形成层间互连，以露出电极表面和相邻隔离屏障。 层间互连可以布置在底层电极的基本上全部的一部分上，例如绝缘栅场效应晶体管（IGFET）源/漏区表面。 蚀刻屏障提供受控的蚀刻，以允许层间互连重叠在隔离屏障上，而不增加寄生电容，相对于传统的接触不对准。 此外，消除重叠的关注允许通过层间互连增加源/漏区表面积的利用。 此外，蚀刻屏障允许层间互连以多个电路器件的带状电极同时显示标称的任何衬底以互连互连漏电流。
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9.发明授权
公开(公告)号：US6104063A
公开(公告)日：2000-08-15
申请号：US942998
申请日：1997-10-02
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L27/088
CPC分类号： H01L29/66492 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A transistor and a transistor fabrication method are presented where a sequence of spacers are formed and partially removed upon sidewall surfaces of the gate conductor to produce a graded junction having a relatively smooth doping profile. The spacers include removable and non-removable structures formed on the sidewall surfaces. The adjacent structures have dissimilar etch characteristics compared to each other and compared to the gate conductor. A first dopant (MDD dopant) and a second dopant (source/drain dopant) are implanted into the semiconductor substrate after the respective formation of the removable structure and the non-removable structure. A third dopant (LDD dopant) is implanted into the semiconductor substrate after the removable layer is removed from between the gate conductor and the non-removable structure (spacer). As a result a graded junction is created having higher concentration regions formed outside of lightly concentration regions, relative to the channel area. Such a doping profile provides superior protection against the hot-carrier effect compared to the traditional LDD structure. The smoother the doping profile, the more gradual the voltage drop across the channel/drain junction. A more gradual voltage drop gives rise to a smaller electric field and reduces the hot-carrier effect. Furthermore, the MDD and source/drain implants are performed first, prior to the LDD implant. This allows high-temperature thermal anneals to be performed first, followed by lower temperature anneals second.
摘要翻译： 提出了晶体管和晶体管制造方法，其中在栅极导体的侧壁表面上形成并部分地去除间隔物序列，以产生具有相对平滑的掺杂分布的梯度结。 间隔件包括形成在侧壁表面上的可移除和不可移除的结构。 相邻的结构具有彼此相比的不同的蚀刻特性并且与栅极导体相比较。 在可移除结构和不可移除结构的相应形成之后，将第一掺杂剂（MDD掺杂剂）和第二掺杂剂（源极/漏极掺杂剂）注入到半导体衬底中。 在可移除层从栅极导体和不可移除结构（间隔物）之间移除之后，将第三掺杂剂（LDD掺杂剂）注入到半导体衬底中。 结果，相对于通道面积产生了在轻微浓度区域之外形成的具有较高浓度区域的分级结。 与传统的LDD结构相比，这种掺杂分布提供了优于热载体效应的保护。 掺杂曲线越平滑，通道/漏极结上的电压降越低。 更加缓慢的电压降会导致较小的电场并降低热载流子效应。 此外，在LDD植入之前，首先执行MDD和源/漏植入。 这允许首先执行高温热退火，其次是较低的温度退火。
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公开(公告)号：US6096639A
公开(公告)日：2000-08-01
申请号：US056835
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895
摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.
摘要翻译： 通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。 在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。 在一些实施例中，钛是用于形成局部互连的合适金属。 用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。 硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。 在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。 在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。
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