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    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MILLICODE STORE ACCESS CHECKING INSTRUCTIONS
    91.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MILLICODE STORE ACCESS CHECKING INSTRUCTIONS 有权
    方法，系统和计算机程序产品用于MILLICODE STORE ACCESS CHECKING说明

    公开(公告)号：US20090210680A1

    公开(公告)日：2009-08-20

    申请号：US12031756

    申请日：2008-02-15

    申请人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

    发明人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3017 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3861

    摘要： A system, method and computer program product for a millicode store access checking instruction are provided. The system includes an operand access control register (OACR) including a test modifier indicator. The system also includes an instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. The system further includes an execution unit to execute the millicode instruction. The execution unit performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception.

    摘要翻译： 提供了一种用于毫存储存储访问检查指令的系统，方法和计算机程序产品。 该系统包括一个操作数访问控制寄存器（OACR），包括一个测试修改器指示符。 该系统还包括用于获取和解码指令的指令单元子系统。 该指令包括一个具有操作数的millicode指令，其中定义了一个地址来检查存储访问异常。 该系统还包括执行毫代码指令的执行单元。 执行单元执行方法。 该方法包括从指令单元子系统接收millicode指令，测试地址处的存储访问异常，就好像将测试修饰符设置为不存在对OACR的更新，并输出用于存储访问异常的测试结果。

    Method and system for managing the result from a translator co-processor in a pipelined processor
    92.
    发明授权
    Method and system for managing the result from a translator co-processor in a pipelined processor 有权
    用于管理流水线处理器中的翻译协处理器的结果的方法和系统

    公开(公告)号：US06671793B1

    公开(公告)日：2003-12-30

    申请号：US09678061

    申请日：2000-10-02

    申请人： Scott B. Swaney ,  Mark S. Farrell ,  John D. MacDougall ,  Hans-Juergen Muenster ,  Charles F. Webb

    发明人： Scott B. Swaney ,  Mark S. Farrell ,  John D. MacDougall ,  Hans-Juergen Muenster ,  Charles F. Webb

    IPC分类号： G06F1516

    CPC分类号： G06F9/3017 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/3879

    摘要： An exemplary embodiment of the invention is a method and system for managing a result returned from a translator co-processor to a recovery unit of a central processor. The computer system has a pipelined computer processor and a pipelined central processor, which executes an instruction set in a hardware controlled execution unit and executes an instruction set in a milli-mode architected state with a millicode sequence of instructions in the hardware controlled execution unit. The central processor initiates a request to the translator co-processor a cycle after decode of a perform translator operation instruction in the millicode sequence. The translator co-processor processes the perform translator operation instruction to generate a perform translator operation result. The translator co-processor returns the results to a recovery unit of the central processor. The recovery unit stores the perform translator operation result in a system register. The request for the perform translator operation result by the central processor is interlocked by a hardware interlock of the recovery unit until the translator co-processor returns the perform translator operation result. The mechanism allows the recovery unit to maintain the correct perform translator operation result with speculative execution and instruction level retry recovery throughout the duration of the perform translator operation.

    摘要翻译： 本发明的示例性实施例是用于管理从翻译器协处理器返回到中央处理器的恢复单元的结果的方法和系统。 计算机系统具有流水线计算机处理器和流水线中央处理器，其执行硬件控制执行单元中的指令集，并且在硬模式执行单元中以毫列指令序列执行毫模式架构状态指令集。 中央处理器在解码执行转换器操作指令之后的一个循环中向转译器协处理器发出一个请求。 翻译协处理器处理执行翻译器操作指令以产生执行转换器操作结果。 翻译协处理器将结果返回到中央处理器的恢复单元。 恢复单元将执行转换器操作结果存储在系统寄存器中。 由中央处理器执行的执行转换器操作结果的请求由恢复单元的硬件互锁互锁，直到转换器协处理器返回执行转换器操作结果。 该机制允许恢复单元在执行转换器操作的整个持续时间内通过推测执行和指令级重试恢复来维持正确的执行转换器操作结果。

    Specialized millicode instruction for range checking
    93.
    发明授权
    Specialized millicode instruction for range checking 失效
    专用millicode指令进行范围检查

    公开(公告)号：US5621909A

    公开(公告)日：1997-04-15

    申请号：US614148

    申请日：1996-03-12

    申请人： Charles F. Webb ,  Mark S. Farrell ,  Wen H. Li

    发明人： Charles F. Webb ,  Mark S. Farrell ,  Wen H. Li

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/00

    CPC分类号： G06F9/30021 ,  G06F9/30094

    摘要： A range check instruction sequence, which performs a logical comparison between two 32-bit values and updates the condition code as a result. It operates identically to the ESA/390 instruction compare logical (CLR) except for the way in which the condition code is set. The new condition code is a function of both the comparison result and the previous condition code. If the first operand is greater than the second operand, the condition code remains unchanged. If the first operand is less than or equal to the second operand, the condition code is set to 2 if it was previously 0 or 1, and is set to 3 if it was previously 2 or 3. This may be understood as advancing the state of the condition code among the groups (0,1), 2, and 3 if the first operand is not greater than the second operand.

    摘要翻译： 范围检查指令序列，其执行两个32位值之间的逻辑比较，并作为结果更新条件代码。 除了条件码的设置方式以外，它与ESA / 390指令比较逻辑（CLR）相同。 新条件代码是比较结果和先前条件代码的函数。 如果第一个操作数大于第二个操作数，则条件代码保持不变。 如果第一个操作数小于或等于第二个操作数，则如果先前为0或1，则条件代码设置为2，如果先前为2或3，则将其设置为3。这可以被理解为推进状态 如果第一个操作数不大于第二个操作数，组（0,1），2和3中的条件代码。

    Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system
    97.
    发明授权
    Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权
    微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取

    公开(公告)号：US08549255B2

    公开(公告)日：2013-10-01

    申请号：US12032041

    申请日：2008-02-15

    申请人： David A. Schroter ,  Mark S. Farrell ,  Jennifer Navarro ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    发明人： David A. Schroter ,  Mark S. Farrell ,  Jennifer Navarro ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30047 ,  G06F12/0862

    摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.

    摘要翻译： 配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访​​问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。 提供了一种方法和计算机程序产品。

    DETERMINATION OF RUNNING STATUS OF LOGICAL PROCESSOR
    98.
    发明申请
    DETERMINATION OF RUNNING STATUS OF LOGICAL PROCESSOR 有权
    确定逻辑处理器的运行状态

    公开(公告)号：US20130014123A1

    公开(公告)日：2013-01-10

    申请号：US13619400

    申请日：2012-09-14

    申请人： Greg A. Dyck ,  Mark S. Farrell ,  Charles W. Gainey ,  Jeffrey P. Kubala ,  Robert R. Rogers ,  Mark A. Wisniewski

    发明人： Greg A. Dyck ,  Mark S. Farrell ,  Charles W. Gainey ,  Jeffrey P. Kubala ,  Robert R. Rogers ,  Mark A. Wisniewski

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52 ,  G06F9/4843 ,  G06F9/5077

    摘要： An embodiment provides for operating an information processing system. An aspect of the invention includes allocating an execution interval to a first logical processor of a plurality of logical processors of the information processing system. The execution interval is allocated for use by the first logical processor in executing instructions on a physical processor of the information processing system. The first logical processor determines that a resource required for execution by the first logical processor is locked by another one of the other logical processors. An instruction is issued by the first logical processor to determine whether a lock-holding logical processor is currently running. The lock-holding logical processor waits to release the lock if it is currently running. A command is issued by the first logical processor to a super-privileged process for relinquishing the allocated execution interval by the first logical processor if the locking holding processor is not running.

    摘要翻译： 实施例提供了操作信息处理系统。 本发明的一个方面包括将执行间隔分配给信息处理系统的多个逻辑处理器的第一逻辑处理器。 执行间隔被分配供第一逻辑处理器在信息处理系统的物理处理器上执行指令时使用。 第一逻辑处理器确定由第一逻辑处理器执行所需的资源被另一个其他逻辑处理器锁定。 由第一逻辑处理器发出指令以确定锁定保持逻辑处理器当前是否正在运行。 锁定逻辑处理器等待释放锁定，如果它当前正在运行。 如果锁定保持处理器不在运行，则由第一逻辑处理器发出命令到超级特权进程以放弃由第一逻辑处理器分配的执行间隔。

    Determination of running status of logical processor
    99.
    发明授权
    Determination of running status of logical processor 有权
    确定逻辑处理器的运行状态

    公开(公告)号：US08276151B2

    公开(公告)日：2012-09-25

    申请号：US11470487

    申请日：2006-09-06

    申请人： Greg A. Dyck ,  Mark S. Farrell ,  Charles W. Gainey ,  Jeffrey P. Kubala ,  Robert R. Rogers ,  Mark A. Wisniewski

    发明人： Greg A. Dyck ,  Mark S. Farrell ,  Charles W. Gainey ,  Jeffrey P. Kubala ,  Robert R. Rogers ,  Mark A. Wisniewski

    IPC分类号： G06F9/46 ,  G06F13/00

    CPC分类号： G06F9/52 ,  G06F9/4843 ,  G06F9/5077

    摘要： A method is provided for a first logical processor to determine a running status of a target logical processor of an information processing system. In such method, an instruction is issued by the first logical processor running on the information processing system for determining whether the target logical processor is running. In response to issuing the instruction, a state descriptor belonging to the target logical processor is queried to determine whether the target logical processor is currently running. A result is then returned to the first logical processor, the result indicating whether or not the target logical processor is currently running.

    摘要翻译： 提供了一种用于第一逻辑处理器来确定信息处理系统的目标逻辑处理器的运行状态的方法。 在这种方法中，在信息处理系统上运行的第一逻辑处理器发出用于确定目标逻辑处理器是否正在运行的指令。 响应于发出指令，查询属于目标逻辑处理器的状态描述符，以确定目标逻辑处理器当前是否正在运行。 然后将结果返回到第一逻辑处理器，结果指示目标逻辑处理器当前是否正在运行。

    PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYNCHRONIZING TOD CLOCKS
    100.
    发明申请
    PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYNCHRONIZING TOD CLOCKS 有权
    执行同步时钟功能的功能指令同步时钟

    公开(公告)号：US20120173917A1

    公开(公告)日：2012-07-05

    申请号：US13402554

    申请日：2012-02-22

    申请人： Eberhard Engler ,  Mark S. Farrell ,  Klaus Meissner ,  Ronald M. Smith, SR. ,  Mark A. Check ,  Evangelyn K. Smith

    发明人： Eberhard Engler ,  Mark S. Farrell ,  Klaus Meissner ,  Ronald M. Smith, SR. ,  Mark A. Check ,  Evangelyn K. Smith

    IPC分类号： G06F1/04 ,  G04C11/00

    CPC分类号： G06F1/14

    摘要： A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

    摘要翻译： 一种用于转向具有物理时钟的计算机系统的时钟（TOD）时钟的系统，方法和计算机程序产品，该物理时钟提供用于执行步进到公共振荡器的操作的时基。 该方法包括在处理单元处接收用于改变用于控制处理单元的TOD时钟偏移值的时钟转向速率的请求，定义为开始时间的函数的TOD时钟偏移量， 基本偏移（b）和转向率（r）。 该单元安排下一个开始时间来更新TOD时钟偏移值。 在预定时间更新TOD时钟偏移值（d）后，将TOD时钟偏移值加到物理时钟值（Tr）值，以获得逻辑TOD时钟值（Tb），其中逻辑TOD时钟 值可调节，而不需要调整振荡器的步进速率。