公开(公告)号：US20090096432A1

公开(公告)日：2009-04-16

申请号：US11907644

申请日：2007-10-16

申请人： Bo-Shih Huang ,  Ming-Dou Ker

发明人： Bo-Shih Huang ,  Ming-Dou Ker

IPC分类号： G05F1/70

CPC分类号： H01L27/0251

摘要： An active loading-reduction device is provided for a circuit. The circuit has functional circuitry coupled to a terminal to receive an alternating voltage. The circuit also has an electrostatic discharge protector that is coupled to the terminal. The active loading-reduction device includes active circuitry that is adapted to be coupled to a power supply to provide a reactance to counteract a reactance provided by the electrostatic discharge protector at the terminal of the circuit.

摘要翻译： 为电路提供一个有源负载减小装置。 电路具有耦合到端子以接收交流电压的功能电路。 电路还具有耦合到端子的静电放电保护器。 有源负载减小装置包括有源电路，其适于耦合到电源以提供电抗以抵消由电路端子处的静电放电保护器提供的电抗。

公开(公告)号：US20090032838A1

公开(公告)日：2009-02-05

申请号：US12113912

申请日：2008-05-01

申请人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L29/747

CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87

摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.

摘要翻译： 本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。

公开(公告)号：US07394630B2

公开(公告)日：2008-07-01

申请号：US10268756

申请日：2002-10-11

申请人： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H01L27/0266

摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.

摘要翻译： 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。

公开(公告)号：US20080151446A1

公开(公告)日：2008-06-26

申请号：US11613193

申请日：2006-12-20

申请人： Ming-Dou Ker ,  Jia-Huei Chen ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jia-Huei Chen ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H9/00

CPC分类号： H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic transistors to bypass the ESD current, avoid the elements of a core circuit being damaged, and solve the non-uniform problem of bypassing the ESD current when ESD occurs. Furthermore, in the ESD protection layout, it only needs to add another doped region on a substrate neighboring to, but not contacting, doped regions of the ESD protection elements and use contacts to connect the added doped region, so as to couple each base of the parasitic transistors together without requiring for additional layout area.

摘要翻译： 提供静电放电（ESD）保护装置及其布局。 偏置导线主要用于将ESD元件内的多个寄生晶体管的每个基极耦合在一起，以便同时触发所有寄生晶体管绕过ESD电流，避免核心电路的元件被损坏，并解决 当ESD发生时绕过ESD电流的非均匀问题。 此外，在ESD保护布局中，仅需要在与ESD保护元件的掺杂区域相邻但不接触的衬底上添加另一个掺杂区域，并使用触点来连接所添加的掺杂区域，以便将 寄生晶体管一起而不需要额外的布局区域。

公开(公告)号：US20080094533A1

公开(公告)日：2008-04-24

申请号：US11894577

申请日：2007-08-21

申请人： Ming-Dou Ker ,  Chih-Kang Deng ,  Wein-Town Sun

发明人： Ming-Dou Ker ,  Chih-Kang Deng ,  Wein-Town Sun

IPC分类号： G02F1/1333 ,  H01L21/332 ,  H01L29/04

CPC分类号： H01L29/7436 ,  G02F1/136204 ,  H01L27/0248 ,  H01L27/0292

摘要： An electrostatic discharge protection device, an electrostatic discharge protection structure, and a manufacturing process of the device are provided. The electrostatic discharge protection device includes at least four doping regions, wherein two adjacent regions are of different types. The electrostatic discharge protection structure includes an electrostatic discharge bus, a plurality of first electrostatic discharge protection devices connecting to the gates of the display transistors and the electrostatic discharge bus, a plurality of second electrostatic discharge protection devices connecting to the source/drain of the transistors and the electrostatic discharge bus, and a plurality of third electrostatic discharge protection devices connecting to the input/output terminals of the drive circuit of the display and the electrostatic discharge bus.

摘要翻译： 提供静电放电保护装置，静电放电保护结构以及该装置的制造过程。 静电放电保护装置包括至少四个掺杂区域，其中两个相邻区域是不同类型的。 静电放电保护结构包括静电放电总线，连接到显示晶体管和静电放电总线的栅极的多个第一静电放电保护器件，连接到晶体管的源极/漏极的多个第二静电放电保护器件 和静电放电总线，以及连接到显示器的驱动电路的输入/输出端子和静电放电总线的多个第三静电放电保护器件。

公开(公告)号：US20080061832A1

公开(公告)日：2008-03-13

申请号：US11649551

申请日：2007-01-03

申请人： Fang-Ling Hu ,  Ming-Dou Ker

发明人： Fang-Ling Hu ,  Ming-Dou Ker

IPC分类号： H03K19/094

CPC分类号： H03K19/00361 ,  H03K19/094

摘要： A circuit configured for providing hot-carrier effect protection, the circuit comprising a first transistor including a first terminal and a second terminal, the first terminal being coupled to a conductive pad, a switch device including a terminal coupled to the conductive pad, and a control circuit configured for keeping the switch at an off state during a receiving mode at which a signal of a first voltage level or a reference level is received at the conductive pad, keeping the switch at the off state during a transmitting mode from which a signal of a second voltage level or the reference level is transmitted at the conductive pad, and keeping the switch at an on state during a transition from the receiving mode when receiving a signal of the first voltage level to the transmitting mode when transmitting a signal having the reference voltage level, wherein during the transition a voltage across the first terminal and the second terminal of the first transistor is maintained at a level below approximately the first voltage level minus the second voltage level.

摘要翻译： 一种配置用于提供热载体效应保护的电路，该电路包括第一晶体管，其包括第一端子和第二端子，第一端子耦合到导电焊盘，开关器件包括耦合到导电焊盘的端子，以及 控制电路，被配置为在接收模式期间将开关保持在断开状态，在接收模式期间，在导电焊盘处接收到第一电压电平或参考电平的信号，在发送模式期间将开关保持在断开状态， 第二电压电平或参考电平在导电焊盘处发送，并且在从接收模式转变期间将开关保持在接通状态，当在发送具有第一电压电平的信号时，当接收到第一电压电平的信号到发送模式时 参考电压电平，其中在转变期间，跨越第一晶体管的第一端子和第二端子的电压保持在a1 电平低于大约第一电压电平减去第二电压电平。

公开(公告)号：US20080054297A1

公开(公告)日：2008-03-06

申请号：US11306212

申请日：2005-12-20

申请人： Ming-Dou Ker ,  Kuo-Chun Hsu

发明人： Ming-Dou Ker ,  Kuo-Chun Hsu

IPC分类号： H01L23/58

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

摘要翻译： 使用双触发硅控制整流器（SCR）的ESD保护电路。 双触发硅控制整流器（SCR）包括N +扩散区域，P +扩散区域，形成在P衬底中的第一N阱区域，第二N阱区域和第三N阱区域。 通过浅沟槽隔离（STI）结构隔离N +扩散区域和P +扩散区域。 N +扩散区域中的两个是N型触发端子。 P +扩散区域中的两个是P型触发端子。

公开(公告)号：US20070290266A1

公开(公告)日：2007-12-20

申请号：US11768785

申请日：2007-06-26

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L23/62 ,  H01L27/102

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US07288449B2

公开(公告)日：2007-10-30

申请号：US11286406

申请日：2005-11-25

申请人： Ming-Dou Ker ,  Hsin-Chyh Hsu ,  Wen-Yu Lo

发明人： Ming-Dou Ker ,  Hsin-Chyh Hsu ,  Wen-Yu Lo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

摘要翻译： 一种制造具有ESD保护和内部电路的第一和第二晶体管的半导体器件的方法。 该方法包括以下步骤：提供衬底，在衬底上形成第一和第二晶体管的栅极，沉积掩模层，并使用一个单一掩模对掩模层进行构图以去除栅极上的掩模层，漏极区域的一部分 的第一晶体管的源极和漏极区域，在没有图案化掩模层的区域下实现ESD注入，去除掩模层并形成栅极的侧壁间隔物，并实现漏极扩散。

公开(公告)号：US07242561B2

公开(公告)日：2007-07-10

申请号：US11033395

申请日：2005-01-12

申请人： Ming-Dou Ker ,  Chein-Ming Lee

发明人： Ming-Dou Ker ,  Chein-Ming Lee

IPC分类号： H02H9/00

CPC分类号： H01L27/0259 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/732 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to an ESD protection with ability to enhance trigger-on speed of a low voltage Triggered PNP (LVTPNP) unit for protecting internal circuits of an integrated circuit from attack of an ESD stress. The ESD protection unit incorporates either detection circuit or power clamp circuit to efficiently trigger on a trigger node as a heavily doped region of LVTPNP devices among an I/O pad, a VDD pin and a VSS pin. As soon as the trigger node of each LVTPNP device receives a trigger signal from either the ESD detection circuit or power clamp circuit, the threshold voltage of the LVTPNP devices are capable of being therefore reduced to enhance trigger-on speed of the LVTPNP devices that discharge ESD current.

摘要翻译： 本发明涉及一种能够增强低电压触发PNP（LVTPNP）单元的触发速度的ESD保护，用于保护集成电路的内部电路免受ESD应力的侵袭。 ESD保护单元包含检测电路或功率钳位电路，以有效地触发触发器节点作为I / O焊盘，VDD引脚和VSS引脚之间的LVTPNP器件的重掺杂区域。 每个LVTPNP器件的触发节点一旦从ESD检测电路或功率钳位电路接收到触发信号，LVTPNP器件的阈值电压就能够被降低，以提高放电的LVTPNP器件的触发速度 ESD电流。