公开(公告)号：US20050175107A1

公开(公告)日：2005-08-11

申请号：US10816724

申请日：2004-04-01

申请人： Arul Thangaraj ,  Vijayanand Aralaguppe ,  Syed Ali

发明人： Arul Thangaraj ,  Vijayanand Aralaguppe ,  Syed Ali

IPC分类号： H04N5/00 ,  H04N7/26 ,  H04N7/12

CPC分类号： H04N21/4305 ,  H04N19/423 ,  H04N19/44 ,  H04N19/70 ,  H04N21/434

摘要： Presented herein is a compressed structure for writing slice group start codes into a start code table, for use with a video decoding system. One or more start codes are written to a start code table. The presentation time information is written to the start code table.

摘要翻译： 这里呈现的是用于将切片组起始码写入起始码表的压缩结构，以用于视频解码系统。 将一个或多个起始码写入起始码表。 演示时间信息被写入起始码表。

公开(公告)号：US5732018A

公开(公告)日：1998-03-24

申请号：US739276

申请日：1996-10-29

申请人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

发明人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

IPC分类号： G11C17/00 ,  G11C5/02 ,  G11C7/10 ,  G11C16/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C5/025 ,  G11C16/28 ,  G11C7/1051

摘要： Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.

摘要翻译： 非易失性集成电路存储器件（例如EEPROM）使用未选择的共享锁存读出放大器来锁存来自在擦除之后要重新编程的存储器单元的数据，并且将锁存数据重新供给到擦除后要被编程的存储器单元， 从而在页编程之后将锁存的数据内部重新编程为擦除的存储器单元。 传送电路和方法用于在共享锁存读出放大器之间传输数据，以允许内部重新编程。 从而提供EEPROM的高速和简化重新编程。

公开(公告)号：US5014097A

公开(公告)日：1991-05-07

申请号：US137782

申请日：1987-12-24

申请人： Reza Kazerounian ,  Syed Ali ,  Boaz Eitan

发明人： Reza Kazerounian ,  Syed Ali ,  Boaz Eitan

IPC分类号： G11C16/30 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07

CPC分类号： H01L27/11526 ,  G11C16/30 ,  H01L27/11546 ,  H02M3/073 ,  H01L27/105 ,  H01L27/115

摘要： An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes a capacitive voltage divider for providing a first voltage proportional to the erase voltage, a reference voltage lead for providing a reference voltage and a control circuit for controlling the voltage multipler circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.