公开(公告)号：US5732018A

公开(公告)日：1998-03-24

申请号：US739276

申请日：1996-10-29

申请人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

发明人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

IPC分类号： G11C17/00 ,  G11C5/02 ,  G11C7/10 ,  G11C16/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C5/025 ,  G11C16/28 ,  G11C7/1051

摘要： Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.

摘要翻译： 非易失性集成电路存储器件（例如EEPROM）使用未选择的共享锁存读出放大器来锁存来自在擦除之后要重新编程的存储器单元的数据，并且将锁存数据重新供给到擦除后要被编程的存储器单元， 从而在页编程之后将锁存的数据内部重新编程为擦除的存储器单元。 传送电路和方法用于在共享锁存读出放大器之间传输数据，以允许内部重新编程。 从而提供EEPROM的高速和简化重新编程。

公开(公告)号：US5737258A

公开(公告)日：1998-04-07

申请号：US638100

申请日：1996-04-26

申请人： Do-Chan Choi ,  Woung-Moo Lee ,  Tae-Sung Jung ,  Syed Ali ,  Ejaz Haq

发明人： Do-Chan Choi ,  Woung-Moo Lee ,  Tae-Sung Jung ,  Syed Ali ,  Ejaz Haq

IPC分类号： G11C17/00 ,  G06F12/00 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C11/401 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C5/025 ,  G11C5/066

摘要： An electrically erasable and programmable nonvolatile memory device (EEPROM) such as a flash memory, is pin compatible with a dynamic random access memory device (DRAM), such that flash memory may be connected to a DRAM bus. Preferably, the flash memory is read and write timing-compatible with the DRAM read and write signals and is also preferably block read and block write timing compatible with DRAM block read and block write signals. The flash memory accepts signals to perform sleep and erase functions from signal lines of a DRAM bus which are not used by a DRAM. In order to perform a block erase, which is a characteristic of flash memory, the device preferably accepts an instruction to perform a block erase from signal lines of a DRAM bus which are not used by a DRAM and a block address for the block erase from the most significant bit address lines of the DRAM bus.

摘要翻译： 诸如闪速存储器的电可擦除和可编程的非易失性存储器件（EEPROM）与动态随机存取存储器件（DRAM）引脚兼容，使得闪速存储器可以连接到DRAM总线。 优选地，闪速存储器是与DRAM读取和写入信号时序兼容的读取和写入，并且还优选地是与DRAM块读取和写入信号兼容的块读取和块写入定时。 闪速存储器接受信号以从未被DRAM使用的DRAM总线的信号线执行睡眠和擦除功能。 为了执行作为闪速存储器的特征的块擦除，设备优选地接受从DRAM不使用的DRAM总线的信号线执行块擦除的指令和用于块擦除的块地址 DRAM总线的最高有效位地址线。

公开(公告)号：US20050040867A1

公开(公告)日：2005-02-24

申请号：US10947892

申请日：2004-09-22

申请人： Ejaz Haq

发明人： Ejaz Haq

IPC分类号： H04L25/06 ,  G01R29/02 ,  G06F13/40 ,  H03K19/0185 ,  H03M9/00 ,  H04L7/00 ,  H04L25/02 ,  H03D13/00

CPC分类号： H03K19/018585 ,  G06F13/4086 ,  H03M9/00 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/061 ,  Y02D10/14 ,  Y02D10/151

摘要： A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

摘要翻译： 本发明的系统使用小的摆动差分源同步电压和定时参考（SSVTR和/ SSVTR）信号来比较同一集成电路同时产生的相同转换速率的单端信号用于高频信号。 每当有效信号由发射集成电路驱动时，SSVTR和/ SSVTR信号切换。 每个信号接收器包括两个比较器，一个用于将信号与SSVTR进行比较，另一个用于将信号与SSVTR进行比较。 当前信号二进制值确定哪个比较器耦合到接收器输出，可选地通过使用具有SSVTR和/ SSVTR的异或逻辑。 接收机中的耦合比较器检测是否发生信号二进制值的变化，直到SSVTR和/ SSVTR改变其二进制值为止。 如果信号转换，则相同的比较器被耦合。 如果不发生转换，则比较器被去耦合。

公开(公告)号：US20060012402A1

公开(公告)日：2006-01-19

申请号：US11176439

申请日：2005-07-06

申请人： Ejaz Haq

发明人： Ejaz Haq

IPC分类号： G01R29/02

CPC分类号： H03K19/018585 ,  G06F13/4086 ,  H03M9/00 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/061 ,  Y02D10/14 ,  Y02D10/151

摘要： A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

公开(公告)号：US20060126745A1

公开(公告)日：2006-06-15

申请号：US10159488

申请日：2002-05-31

申请人： Ejaz Haq ,  James Slager

发明人： Ejaz Haq ,  James Slager

IPC分类号： H04L25/00

CPC分类号： H04L25/061 ,  H04L25/0286

摘要： A system and method increases signal strength at a receiver in transmission lines with high attenuation. The system comprises a transmitter for transmitting a pair of complementary oscillating voltage and timing references and a signal across transmission lines to a receiver. Since the references oscillate every bit time, the references do not suffer from the lone pulse problem but do suffer from attenuation. Since the signal may remain in a single state for several bit times, the signal may suffer from the lone pulse problem. The receiver maintains the references and the signal oscillating about a reference voltage, and compares the signal against the references. Based on the comparison, the receiver determines whether the current signal state has changed since the last signal state. Since the receiver compares one signal that suffers from the lone pulse problem against a reference that does not, signal strength is improved. Further, to improve signal strength, the transmitter can include a pulse driver to drive further the signal in a particular direction while the signal is transitioning.

摘要翻译： 系统和方法在具有高衰减的传输线路中的接收机处增加信号强度。 该系统包括用于将一对互补的振荡电压和定时参考以及跨传输线的信号传输到接收器的发射器。 由于引用每个位时间振荡，所以参考文献不会受到单个脉冲问题的困扰，而是会遭受衰减。 由于信号可能保持在单个状态几比特时间，所以该信号可能遭受单个脉冲问题。 接收器保持参考电压和信号围绕参考电压振荡，并将信号与参考电压进行比较。 基于比较，接收机确定自上一个信号状态以来当前信号状态是否已经改变。 由于接收机将单个脉冲问题的一个信号与不参考的参考信号进行比较，所以信号强度得到改善。 此外，为了提高信号强度，发射机可以包括脉冲驱动器，以在信号转换时进一步驱动特定方向的信号。

公开(公告)号：US20050242847A1

公开(公告)日：2005-11-03

申请号：US11176799

申请日：2005-07-06

申请人： Ejaz Haq

发明人： Ejaz Haq

IPC分类号： H04L25/06 ,  G01R29/02 ,  G06F13/40 ,  H03K19/0185 ,  H03M9/00 ,  H04L7/00 ,  H04L25/02

CPC分类号： H03K19/018585 ,  G06F13/4086 ,  H03M9/00 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/061 ,  Y02D10/14 ,  Y02D10/151

摘要： A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.