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    Nonvolatile semiconductor memory which is connectable to a DRAM bus
    1.
    发明授权
    Nonvolatile semiconductor memory which is connectable to a DRAM bus 失效
    可连接到DRAM总线的非易失性半导体存储器

    公开(公告)号：US5737258A

    公开(公告)日：1998-04-07

    申请号：US638100

    申请日：1996-04-26

    申请人： Do-Chan Choi ,  Woung-Moo Lee ,  Tae-Sung Jung ,  Syed Ali ,  Ejaz Haq

    发明人： Do-Chan Choi ,  Woung-Moo Lee ,  Tae-Sung Jung ,  Syed Ali ,  Ejaz Haq

    IPC分类号： G11C17/00 ,  G06F12/00 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C11/401 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16

    CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C5/025 ,  G11C5/066

    摘要： An electrically erasable and programmable nonvolatile memory device (EEPROM) such as a flash memory, is pin compatible with a dynamic random access memory device (DRAM), such that flash memory may be connected to a DRAM bus. Preferably, the flash memory is read and write timing-compatible with the DRAM read and write signals and is also preferably block read and block write timing compatible with DRAM block read and block write signals. The flash memory accepts signals to perform sleep and erase functions from signal lines of a DRAM bus which are not used by a DRAM. In order to perform a block erase, which is a characteristic of flash memory, the device preferably accepts an instruction to perform a block erase from signal lines of a DRAM bus which are not used by a DRAM and a block address for the block erase from the most significant bit address lines of the DRAM bus.

    摘要翻译： 诸如闪速存储器的电可擦除和可编程的非易失性存储器件（EEPROM）与动态随机存取存储器件（DRAM）引脚兼容，使得闪速存储器可以连接到DRAM总线。 优选地，闪速存储器是与DRAM读取和写入信号时序兼容的读取和写入，并且还优选地是与DRAM块读取和写入信号兼容的块读取和块写入定时。 闪速存储器接受信号以从未被DRAM使用的DRAM总线的信号线执行睡眠和擦除功能。 为了执行作为闪速存储器的特征的块擦除，设备优选地接受从DRAM不使用的DRAM总线的信号线执行块擦除的指令和用于块擦除的块地址 DRAM总线的最高有效位地址线。

    Self-contained reprogramming nonvolatile integrated circuit memory devices and methods
    2.
    发明授权
    Self-contained reprogramming nonvolatile integrated circuit memory devices and methods 失效
    独立的重新编程非易失性集成电路存储器件和方法

    公开(公告)号：US5732018A

    公开(公告)日：1998-03-24

    申请号：US739276

    申请日：1996-10-29

    申请人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

    发明人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

    IPC分类号： G11C17/00 ,  G11C5/02 ,  G11C7/10 ,  G11C16/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  G11C11/34 ,  G11C7/00

    CPC分类号： G11C5/025 ,  G11C16/28 ,  G11C7/1051

    摘要： Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.

    摘要翻译： 非易失性集成电路存储器件（例如EEPROM）使用未选择的共享锁存读出放大器来锁存来自在擦除之后要重新编程的存储器单元的数据，并且将锁存数据重新供给到擦除后要被编程的存储器单元， 从而在页编程之后将锁存的数据内部重新编程为擦除的存储器单元。 传送电路和方法用于在共享锁存读出放大器之间传输数据，以允许内部重新编程。 从而提供EEPROM的高速和简化重新编程。

    Systems and methods for distinguishing between memory types
    3.
    发明授权
    Systems and methods for distinguishing between memory types 失效
    用于区分内存类型的系统和方法

    公开(公告)号：US06012122A

    公开(公告)日：2000-01-04

    申请号：US769588

    申请日：1996-12-18

    申请人： Do-Chan Choi ,  Tae-Sung Jung ,  Oh-Seung Kwon

    发明人： Do-Chan Choi ,  Tae-Sung Jung ,  Oh-Seung Kwon

    IPC分类号： G11C11/401 ,  G06F12/00 ,  G06F12/06 ,  G11C7/20 ,  G11C11/4072

    CPC分类号： G11C11/4072 ,  G11C7/20

    摘要： A plurality of memory types are distinguished from one another in memory systems containing a plurality of memory types by applying an input signal to the memory system containing the plurality of memory types and detecting differing outputs from the plurality of memory types during a predetermined time period after the input signal is applied. Extended data output (EDO), dynamic random access memories (DRAM) are thereby distinguished from fast page mode (F/P) DRAM. Similarly, nonvolatile memory such as DRAM interface flash memory (DIFM) are distinguished from conventional DRAMs.

    摘要翻译： 多个存储器类型在包含多种存储器类型的存储器系统中通过将输入信号施加到包含多种存储器类型的存储器系统并且在预定时间段之后的多个存储器类型中检测不同的输出而彼此区分开 输入信号被施加。 扩展数据输出（EDO），动态随机存取存储器（DRAM）从而与快速页模式（F / P）DRAM区分开。 类似地，诸如DRAM接口闪存（DIFM）的非易失性存储器与常规DRAM不同。

    System and method of charging for user traffic except signaling a wireless communication system
    6.
    发明申请
    System and method of charging for user traffic except signaling a wireless communication system 有权
    无线通信系统的信号发送系统和用户流量计费方法

    公开(公告)号：US20050227667A1

    公开(公告)日：2005-10-13

    申请号：US11075723

    申请日：2005-03-10

    申请人： Tae-Sung Jung

    发明人： Tae-Sung Jung

    IPC分类号： H04L12/14 ,  H04L12/24 ,  H04M11/00

    CPC分类号： H04L41/00

    摘要： A system and method of charging for user traffic without including signaling costs in a wireless communication system is provided. In a system and method of charging a user equipment (UE) in a gateway node in a mobile communication system having a serving support node within a radio network connected to the UE and the gateway node for connecting the radio network to a home server in an external network, the gateway node acquires from the external network the address of a home server that provides a service requested by the UE, stores the home server address, clears charging information collected with respect to signaling generated prior to the allocation of the home server address, and re-collects charging information about the service that the UE receives.

    摘要翻译： 提供了一种用于在无线通信系统中不包括信令成本的用户业务的收费的系统和方法。 在具有连接到UE的无线电网络内的具有服务支持节点的移动通信系统中的网关节点中的用户设备（UE）的系统和方法以及用于将无线电网络连接到家庭服务器的网关节点 外部网络，网关节点从外部网络获取提供UE请求的服务的家庭服务器的地址，存储家庭服务器地址，清除与分配家庭服务器地址之前生成的信令相关的收费信息 并重新收集关于UE接收的业务的收费信息。

    Sense amplifier for semiconductor memory device
    7.
    发明授权
    Sense amplifier for semiconductor memory device 失效
    用于半导体存储器件的检测放大器

    公开(公告)号：US5796273A

    公开(公告)日：1998-08-18

    申请号：US650399

    申请日：1996-05-20

    申请人： Tae-Sung Jung ,  Jung-Hoon Park

    发明人： Tae-Sung Jung ,  Jung-Hoon Park

    IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C11/407 ,  G11C11/419 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G01R19/00

    CPC分类号： G11C11/5621 ,  G11C7/062 ,  G11C7/06

    摘要： A sense amplifier has a pair of output terminals and a first pair of pull-up transistors. A second pair of transistors is connected between the output terminals and a pull-down node. The gate electrodes of the second pair are cross-coupled to the output terminals. A third pair of transistors is connected between the output terminals and the pull-down node and have gate electrodes coupled to input potentials. A fourth pair of transistors is connected between the output terminals and the pull-down node and also have gate electrodes coupled to input potentials.

    摘要翻译： 读出放大器具有一对输出端和第一对上拉晶体管。 第二对晶体管连接在输出端子和下拉节点之间。 第二对的栅电极交叉耦合到输出端。 第三对晶体管连接在输出端子和下拉节点之间，并具有耦合到输入电位的栅电极。 第四对晶体管连接在输出端子和下拉节点之间，并且还具有耦合到输入电位的栅电极。

    Nonvolatile semiconductor member with different pass potential applied to the first two adjacent word
    8.
    发明授权
    Nonvolatile semiconductor member with different pass potential applied to the first two adjacent word 失效
    具有不同通过电位的非易失性半导体元件施加到前两个相邻字

    公开(公告)号：US5621684A

    公开(公告)日：1997-04-15

    申请号：US623793

    申请日：1996-03-29

    申请人： Tae-Sung Jung

    发明人： Tae-Sung Jung

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C16/08

    摘要： A nonvolatile memory with NAND structured cells includes a plurality of cell units formed of a plurality of series-connected memory transistors, each having a source, a drain, a floating gate and a control gate. A row decoder is connected to the control gates of each memory transistor selects at east one of the cell units and one of the memory transistors within the selected cell unit. During programming, the row decoder causes a different pass potential to be applied to nonselected word lines adjacent to selected word lines than that which is applied to other nonselected word lines. Adjacent memory transistors respectively connected to the drain and source of the selected memory transistor on an unselected bit line are thus rendered nonconductive. Thereafter, the selected memory transistor is charged to a local boost potential when a programming potential is applied thereto, and a variation of its threshold voltage is prevented.

    摘要翻译： 具有NAND结构单元的非易失性存储器包括由多个串联连接的存储晶体管形成的多个单元单元，每个单元具有源极，漏极，浮置栅极和控制栅极。 行解码器连接到每个存储晶体管的控制栅极，在单元单元的一个单元单元和所选单元单元内的一个存储晶体管中选择。 在编程期间，行解码器将不同的通过电位施加到与所选字线相邻的非选择字线，而不是应用于其他非选择字线的那些。 因此，分别连接到未选定位线上的所选存储晶体管的漏极和源极的相邻存储器晶体因此变得不导电。 此后，当向其施加编程电位时，所选择的存储晶体管被充电到局部升压电位，并且防止其阈值电压的变化。

    System and method for assigning a mobile IP to a mobile node
    10.
    发明授权
    System and method for assigning a mobile IP to a mobile node 有权

    公开(公告)号：US07512687B2

    公开(公告)日：2009-03-31

    申请号：US10002534

    申请日：2001-11-01

    申请人： Tae-Sung Jung

    发明人： Tae-Sung Jung

    IPC分类号： G06F15/16

    CPC分类号： H04L12/4641 ,  H04L63/0272 ,  H04W8/10 ,  H04W80/04

    摘要： Disclosed is a system providing a VPN service by connecting a VPN (virtual Private Network) to a mobile communication network. A home agent (HA) stores location information of a mobile node (MN) and information on whether the MN is registered in the VPN. A foreign agent (FA) transmits a location registration request message to the HA by receiving location registration information of the MN, and transmits data to an ISP (Internet Service Provider) router in the same subnet upon receiving a VPN service request. A server provides the VPN service and a router network connects the VPN to the FA. The router network includes a server for searching an edge IP router in the network using an address of the FA. The HA prevents an MN from accepting a call request received from a specific node in an IP network while the MN is performing a VPN service.