公开(公告)号：US07460406B2

公开(公告)日：2008-12-02

申请号：US12023317

申请日：2008-01-31

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

公开(公告)号：US20080244368A1

公开(公告)日：2008-10-02

申请号：US11694951

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： G06F11/07 ,  G06F12/00

CPC分类号： G11C11/5642 ,  G06F11/1072 ,  G11C29/00

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility during the iterative decoding that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以执行使用基于从系统读取的数据中的误差水平的可调节温度参数的模拟退火以辅助迭代解码过程。 模拟退火可以将随机性作为噪声引入到基于度量的解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性在迭代解码期间增加了灵活性，这允许在数据可能不可校正的情况下可能更快的收敛时间和收敛。

公开(公告)号：US20080244367A1

公开(公告)日：2008-10-02

申请号：US11694950

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： G06F11/07 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7209 ,  H03M13/1102

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility during the iterative decoding that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以执行使用基于从系统读取的数据中的误差水平的可调节温度参数的模拟退火以辅助迭代解码过程。 模拟退火可以将随机性作为噪声引入到基于度量的解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性在迭代解码期间增加了灵活性，这允许在数据可能不可校正的情况下可能更快的收敛时间和收敛。

公开(公告)号：US20080237698A1

公开(公告)日：2008-10-02

申请号：US11691858

申请日：2007-03-27

申请人： Nima Mokhlesi ,  Roy Scheuerlein

发明人： Nima Mokhlesi ,  Roy Scheuerlein

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11556 ,  H01L27/11568

摘要： A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

摘要翻译： 单片三维NAND串包括位于第二存储单元上的第一存储单元。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

公开(公告)号：US20080198664A1

公开(公告)日：2008-08-21

申请号：US11694989

申请日：2007-03-31

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/36

CPC分类号： G11C8/10 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting threshold voltage distributions and programs non-volatile storage elements to at least two ending threshold voltage distributions.

摘要翻译： 一组非易失性存储元件被擦除为擦除的阈值电压分布。 执行多遍编程处理，其将该非易失性存储元件组从擦除的阈值电压分布编程到设定的有效数据阈值电压分布。 每个编程遍具有一个或多个起始阈值电压分布，并将非易失性存储元件编程为至少两个结束阈值电压分布。

公开(公告)号：US20080158992A1

公开(公告)日：2008-07-03

申请号：US11618793

申请日：2006-12-30

申请人： Deepak Chandra Sekar ,  Nima Mokhlesi

发明人： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/565

摘要： A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

摘要翻译： 可以应用身体偏差以优化性能的非易失性存储系统。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US20080158974A1

公开(公告)日：2008-07-03

申请号：US11618578

申请日：2006-12-29

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/06 ,  G11C29/00

CPC分类号： G11C29/52 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.

摘要翻译： 由于存储在相邻浮动栅极（或其他电荷存储元件）中的电荷的电场的耦合，可能会发生存储在非易失性存储单元的浮动栅极（或其他电荷存储元件）上的视在电荷的变化， 。 为了解决这种耦合，对于目标存储器单元的读取处理将向邻近的存储器单元（或其他存储单元）提供补偿，以便减少相邻存储单元对目标存储器单元具有的耦合效应。 所施加的补偿基于相邻存储单元的条件。 为了应用正确的补偿，读取过程将至少部分地将相邻存储器单元的读取操作与目标存储器单元的读取操作混合。

公开(公告)号：US20080090351A1

公开(公告)日：2008-04-17

申请号：US11550386

申请日：2006-10-17

申请人： Nima Mokhlesi ,  Masaaki Higashitani

发明人： Nima Mokhlesi ,  Masaaki Higashitani

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  H01L21/28114 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42376

摘要： A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.

摘要翻译： 用于非易失性存储系统的选择栅极结构包括独立驱动的选择栅极和耦合电极。 耦合电极与NAND串中的字线相邻，并且具有施加的电压，其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。 特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。 当使用非相邻字线进行编程时，施加降低的电压。 电压也可以根据其他编程标准设定。 选择栅极由第一导电区域提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

公开(公告)号：US20080084754A1

公开(公告)日：2008-04-10

申请号：US11537548

申请日：2006-09-29

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C8/10 ,  G11C11/5642 ,  G11C16/3418

摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where adjacent memory cells are programmed after a selected memory cell. To account for the shift in apparent charge, one or more compensations are applied when reading storage elements of a selected word line based on the charge stored by storage elements of other word lines. Efficient compensation techniques are provided by reverse reading blocks (or portions thereof) of memory cells. By reading in the opposite direction of programming, the information needed to apply (or select the results of) an appropriate compensation when reading a selected cell is determined during the actual read operation for the adjacent word line rather than dedicating a read operation to determine the information.

摘要翻译： 由于存储在相邻（或其他）电荷存储区域中的电荷的电场耦合，可能会发生由非易失性存储单元中的诸如浮动栅极之类的电荷存储区域存储的表观电荷的变化。 尽管不是排他地，但是在选择的存储单元之后对相邻存储单元进行编程的情况下，效果最明显。 为了考虑视在电荷的偏移，基于由其他字线的存储元件存储的电荷来读取所选字线的存储元件时，应用一个或多个补偿。 高效补偿技术由存储单元的反向读取块（或其部分）提供。 通过以相反的编程方向读取，在读取所选单元格期间应用（或选择结果）所需的信息在相邻字线的实际读取操作期间被确定，而不是专用于读取操作来确定 信息。

公开(公告)号：US07349264B2

公开(公告)日：2008-03-25

申请号：US11321996

申请日：2005-12-28

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

摘要翻译： 本发明提供了一种用于感测存储器单元的方案。 所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。 存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。 位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值 到达目前，当前基本上关闭。 特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。