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    Memory System Topologies Including A Memory Die Stack
    91.
    发明申请
    Memory System Topologies Including A Memory Die Stack 有权

    公开(公告)号：US20210375351A1

    公开(公告)日：2021-12-02

    申请号：US17323889

    申请日：2021-05-18

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

    Protocol including a command-specified timing reference signal
    92.
    发明申请
    Protocol including a command-specified timing reference signal 有权

    公开(公告)号：US20210279191A1

    公开(公告)日：2021-09-09

    申请号：US17191469

    申请日：2021-03-03

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Thomas J. Giovannini

    IPC: G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22

    Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

    Memory system topologies including a memory die stack
    94.
    发明授权
    Memory system topologies including a memory die stack 有权

    公开(公告)号：US11043258B2

    公开(公告)日：2021-06-22

    申请号：US16842368

    申请日：2020-04-07

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C7/00 ,  G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/18 ,  H01L23/00

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

    MEMORY WITH ALTERNATIVE COMMAND INTERFACES
    95.
    发明申请
    MEMORY WITH ALTERNATIVE COMMAND INTERFACES 有权

    公开(公告)号：US20210011876A1

    公开(公告)日：2021-01-14

    申请号：US16942970

    申请日：2020-07-30

    Applicant: Rambus Inc.

    Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

    IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16

    Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

    Memory error detection
    97.
    发明授权
    Memory error detection 有权

    公开(公告)号：US10558520B2

    公开(公告)日：2020-02-11

    申请号：US15838161

    申请日：2017-12-11

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Craig E. Hampel

    IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

    On-die termination of address and command signals
    98.
    发明授权
    On-die termination of address and command signals 有权

    公开(公告)号：US10510388B2

    公开(公告)日：2019-12-17

    申请号：US16174180

    申请日：2018-10-29

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Kyung Suk Oh

    IPC: G11C5/06 ,  G11C7/22 ,  G11C29/02 ,  G11C11/4063 ,  G11C5/04 ,  G11C11/4097 ,  G11C7/18 ,  G11C5/02

    Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

    Protocol including a command-specified timing reference signal
    99.
    发明申请
    Protocol including a command-specified timing reference signal 审中-公开

    公开(公告)号：US20190340143A1

    公开(公告)日：2019-11-07

    申请号：US16405421

    申请日：2019-05-07

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Thomas J. Giovannini

    IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G06F12/00

    Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

    Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
    100.
    发明申请
    Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device 审中-公开

    公开(公告)号：US20190259447A1

    公开(公告)日：2019-08-22

    申请号：US16214986

    申请日：2018-12-10

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4076 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4094 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065 ,  H01L25/10

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

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