公开(公告)号：US20130041494A1

公开(公告)日：2013-02-14

申请号：US13204955

申请日：2011-08-08

申请人： Christopher P. Ausschnitt ,  Timothy A. Brunner ,  Allen H. Gabor ,  Oleg Gluschenkov ,  Vinayan C. Menon

发明人： Christopher P. Ausschnitt ,  Timothy A. Brunner ,  Allen H. Gabor ,  Oleg Gluschenkov ,  Vinayan C. Menon

IPC分类号： G06F19/00

CPC分类号： G05B19/401 ,  G05B2219/2602 ,  G05B2219/45031

摘要： Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.

摘要翻译： 通过在一个或多个处理步骤之前和之后的光刻处理步骤中测量衬底对准数据来确定由于一个或多个处理步骤导致的衬底的变形。 通过将计算的对准数据差异与在数据库中累积的先前数据进行比较来识别对准数据差异中的任何异常模式。 通过将异常模式与先前识别的针对对准数据差异的工具特定模式进行比较，可以识别引入异常模式和/或异常处理性质的处理步骤，并且可以采取适当的过程控制措施来纠正任何异常 在所识别的处理步骤中。

公开(公告)号：US20130005126A1

公开(公告)日：2013-01-03

申请号：US13608422

申请日：2012-09-10

申请人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

发明人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

IPC分类号： H01L21/425

CPC分类号： H01L21/823857

摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

摘要翻译： 提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。 所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从 聚束束植入步骤后的结构。

公开(公告)号：US08237278B2

公开(公告)日：2012-08-07

申请号：US12619002

申请日：2009-11-16

申请人： Oleg Gluschenkov ,  Yunsheng Song ,  Tso-Hui Ting ,  Ping-Chuan Wang

发明人： Oleg Gluschenkov ,  Yunsheng Song ,  Tso-Hui Ting ,  Ping-Chuan Wang

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L22/20 ,  H01L23/13 ,  H01L23/481 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/15311 ,  H05K1/0286 ,  H05K1/142 ,  H05K2201/2018 ,  H05K2203/1572 ,  Y10T29/49117 ,  H01L2924/00

摘要： A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

摘要翻译： 模块化插入器包括多个插入器单元，其被组合以提供两个半导体芯片之间的完整的电连接。 多个插入单元中的至少一些可以被具有替代配置的其它插入单元替代，以便能够通过模块化插入器选择要连接的半导体芯片的不同功能部件。 连接到位于相邻插入单元周围的导电金属焊盘和半导体芯片的上部或下部的结合结构可以在相邻插入单元之间提供电连接。 可以通过在衬底中形成贯穿衬底通孔（TSV）来形成插入器单元，在衬底上形成图案化的导电结构，并将衬底切割成插入层。

公开(公告)号：US20120146092A1

公开(公告)日：2012-06-14

申请号：US13397860

申请日：2012-02-16

申请人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

发明人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

IPC分类号： H01L27/092

CPC分类号： H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

摘要翻译： 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

公开(公告)号：US07923782B2

公开(公告)日：2011-04-12

申请号：US10708378

申请日：2004-02-27

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07900167B2

公开(公告)日：2011-03-01

申请号：US11923131

申请日：2007-10-24

申请人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： G06F17/50

CPC分类号： H01L29/7371 ,  H01L29/0826 ,  H01L29/161

摘要： Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

摘要翻译： 公开了具有窄的基本上无间隙的SIC基座的改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管）的设计结构，其具有极小的外部基极的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。

公开(公告)号：US07824989B2

公开(公告)日：2010-11-02

申请号：US12050596

申请日：2008-03-18

申请人： Huilong Zhu ,  Oleg Gluschenkov

发明人： Huilong Zhu ,  Oleg Gluschenkov

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/7624 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.

摘要翻译： 一种用于形成场效应晶体管（FET）器件的方法包括在半导体衬底上形成栅极导体; 形成源极区域，所述源极区域具有在所述栅极导体下方重叠并延伸的源极延伸部; 以及形成漏极区域，所述漏极区域具有漏极延伸部，所述漏极延伸部沿所述栅极的宽度在选定位置处重叠并延伸到所述栅极导体下方; 并且所述漏极区域还包括对应于所述漏极延伸部不重叠并在所述栅极导体下方延伸的区域的多个凹陷区域，其中所述多个凹陷区域仅形成在所述漏极区域中。

公开(公告)号：US07719005B2

公开(公告)日：2010-05-18

申请号：US11672059

申请日：2007-02-07

申请人： Ishtiaq Ahsan ,  Oleg Gluschenkov

发明人： Ishtiaq Ahsan ,  Oleg Gluschenkov

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L22/20

摘要： According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.

摘要翻译： 根据本发明，公开了一种使用该装置来表征和监测图案密度对半导体热吸收的依赖性的热检测装置和方法。 一个或多个装置可以设置在测试晶片的管芯上。 热检测装置包括具有基本上位于硅衬底的中心的测试结构的硅衬底。 具有各种构造的多晶硅，硅和氧化物的框形结构在硅衬底上形成并置布置。 对测试晶片进行快速热处理，并且测量至少一个测试结构的电阻，并将测量的至少一个测试结构的电阻列表成至少一个管芯的热吸收值。

公开(公告)号：US20090108300A1

公开(公告)日：2009-04-30

申请号：US11923131

申请日：2007-10-24

申请人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L29/737

CPC分类号： H01L29/7371 ,  H01L29/0826 ,  H01L29/161

摘要： Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

摘要翻译： 公开了具有窄的基本上无间隙的SIC基座的改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管）的设计结构，其具有极小的外部基极的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。

公开(公告)号：US07521760B2

公开(公告)日：2009-04-21

申请号：US11775607

申请日：2007-07-10

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00 ,  H01L47/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。