公开(公告)号：US11387244B2

公开(公告)日：2022-07-12

申请号：US16849600

申请日：2020-04-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Senaka Kanakamedala ,  Fei Zhou ,  Yao-Sheng Lee

IPC: H01L27/11556 ,  H01L29/423 ,  H01L23/538 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

公开(公告)号：US11322509B2

公开(公告)日：2022-05-03

申请号：US17001270

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L21/8239 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10

Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.

公开(公告)号：US20220130853A1

公开(公告)日：2022-04-28

申请号：US17082629

申请日：2020-10-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L29/04 ,  H01L29/45 ,  H01L21/285 ,  H01L21/02 ,  H01L25/00

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.

公开(公告)号：US11309301B2

公开(公告)日：2022-04-19

申请号：US16886221

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Adarsh Rajashekhar

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US11302716B2

公开(公告)日：2022-04-12

申请号：US16876816

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli Zhang ,  Fei Zhou ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11585 ,  H01L23/528 ,  H01L23/522

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US11145628B1

公开(公告)日：2021-10-12

申请号：US16825397

申请日：2020-03-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Senaka Kanakamedala ,  Fei Zhou

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

公开(公告)号：US20210305266A1

公开(公告)日：2021-09-30

申请号：US16833378

申请日：2020-03-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yao-Sheng Lee ,  Senaka KANAKAMEDALA ,  Raghuveer S. Makala ,  Johann ALSMEIER

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L21/768

Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.

公开(公告)号：US10985172B2

公开(公告)日：2021-04-20

申请号：US16251854

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Yanli Zhang ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L27/115 ,  H01L27/11568 ,  H01L27/1159 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20210036019A1

公开(公告)日：2021-02-04

申请号：US16910638

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.

公开(公告)号：US10818542B2

公开(公告)日：2020-10-27

申请号：US16362895

申请日：2019-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11565 ,  H01L27/11519

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.