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公开(公告)号：US20210082515A1
公开(公告)日：2021-03-18
申请号：US17102712
申请日：2020-11-24
发明人： Ching-Huang Lu , Ashish Baraskar , Vinh Diep
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34 , H01L27/11582 , H01L27/1157
摘要： Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.
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2.发明申请公开(公告)号：US20200265897A1
公开(公告)日：2020-08-20
申请号：US16280297
申请日：2019-02-20
发明人： Ching-Huang Lu , Ashish Baraskar , Vinh Diep
IPC分类号： G11C16/14 , G11C16/04 , G11C16/34 , H01L27/11578 , H01L27/1157
摘要： Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.
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公开(公告)号：US10115730B1
公开(公告)日：2018-10-30
申请号：US15626766
申请日：2017-06-19
发明人： Ashish Baraskar , Naohiro Hosoda , Yanli Zhang , Raghuveer S. Makala , Hiroyuki Tanaka , Ryo Nakamura , Tadashi Nakamura
IPC分类号： H01L27/115 , H01L27/11556 , H01L27/11582 , H01L27/11524 , H01L27/1157 , H01L21/265
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening and contacting a top surface of the semiconductor surface, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure.
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公开(公告)号：US20180308556A1
公开(公告)日：2018-10-25
申请号：US15495178
申请日：2017-04-24
发明人： Ashish Baraskar , Liang Pang , Yingda Dong , Ching-Huang Lu , Nan Lu , Hong-Yan Chen
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/28 , G11C16/32 , G11C16/3459
摘要： A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.
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公开(公告)号：US20180033794A1
公开(公告)日：2018-02-01
申请号：US15221269
申请日：2016-07-27
发明人： Ashish Baraskar , Liang Pang , Yanli Zhang , Raghuveer Makala , Yingda Dong
IPC分类号： H01L27/115 , H01L27/105
CPC分类号： H01L27/1157 , H01L27/1052 , H01L27/11565 , H01L27/11582 , H01L29/7926
摘要： A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.
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公开(公告)号：US09673216B1
公开(公告)日：2017-06-06
申请号：US15212682
申请日：2016-07-18
发明人： Ashish Baraskar , Liang Pang , Yingda Dong , Ching-huang Lu
IPC分类号： H01L27/115 , H01L21/311 , H01L27/11582 , H01L21/02 , H01L21/28 , H01L27/11556
CPC分类号： H01L27/11582 , H01L21/02063 , H01L21/02164 , H01L21/0217 , H01L21/02532 , H01L21/02636 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11556 , H01L27/1157
摘要： Disclosed herein are methods of forming memory cell films in 3D memory. An opening having a sidewall may be formed through a stack of alternating layers of silicon oxide and silicon nitride. Bird's beaks may be formed in the silicon nitride at interfaces with the silicon oxide. In one aspect, bird's beaks are formed using a wet SiN etch. In one aspect, bird's beaks are formed by oxidizing SiN. A dilute hydrofluoric acid (DHF) clean may be performed within the opening after forming the bird's beaks in the silicon nitride. A memory cell film may be formed in the opening after performing the DHF clean. The memory cell film is straight, or nearly straight, from top to bottom in a memory hole. The memory cell film is not as susceptible to parasitic charge trapping as a memory cell film having a wavy contour. Therefore, neighbor WL interference may be reduced.
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公开(公告)号：US11495613B2
公开(公告)日：2022-11-08
申请号：US16984950
申请日：2020-08-04
IPC分类号： H01L27/11582 , H01L23/522 , H01L27/11565 , H01L27/1157
摘要： A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.
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公开(公告)号：US20210202022A1
公开(公告)日：2021-07-01
申请号：US16728716
申请日：2019-12-27
发明人： Ashish Baraskar , Henry Chin , Ching-Huang Lu
摘要： A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.
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9.发明授权公开(公告)号：US10964402B1
公开(公告)日：2021-03-30
申请号：US16794614
申请日：2020-02-19
发明人： Han-Ping Chen , Henry Chin , Ashish Baraskar
摘要： Techniques are described for reprogramming memory cells to tighten threshold voltage distributions and improve data retention. In one aspect, the memory cells of a word line WLn are reprogrammed after programming of memory cells of an adjacent, later-programmed word line WLn+1. The reprogramming can be limited to lower state memory cells of WLn which are adjacent to lower state memory cells of WL+1. A program pulse magnitude used in the reprogramming can be tailored to the data states of the WLn memory cell and the adjacent, WLn+1 memory cell. In some cases, the program pulse magnitudes can be grouped to reduce the implementation complexity and time. The reprogramming can occur after an initial program operation has completed, during an idle time of a control circuit.
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10.发明授权公开(公告)号：US10068651B1
公开(公告)日：2018-09-04
申请号：US15621215
申请日：2017-06-13
发明人： Vinh Diep , Wei Zhao , Ashish Baraskar , Ching-Huang Lu , Yingda Dong
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient which can lead to a disturb of the select gate transistors. One approach involves applying a voltage at an intermediate level to the source and/or drain ends of the memory strings, before increasing the voltage from the intermediate level to a peak erase level. Another approach involves driving the word line voltages at a negative level and then at a higher level to down couple and then up couple the channel voltages. The techniques may be adjusted depending on whether the word lines are at a positive floating voltage at a start of the erase operation, and based on a level of the floating voltage.
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