公开(公告)号：US07190000B2

公开(公告)日：2007-03-13

申请号：US10915958

申请日：2004-08-11

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L29/04

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US07109104B2

公开(公告)日：2006-09-19

申请号：US10665122

申请日：2003-09-22

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

公开(公告)号：US20060203175A1

公开(公告)日：2006-09-14

申请号：US10565837

申请日：2004-06-11

申请人： Young-Goo Song ,  Hyang-Shik Kong ,  Sung-Man Kim

发明人： Young-Goo Song ,  Hyang-Shik Kong ,  Sung-Man Kim

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339 ,  G02F1/1341

摘要： An array substrate (100a) includes a transparent substrate (304), a first insulation layer (306) and a pixel electrode (103). The transparent substrate (304) includes a display region (DR) that displays an image, a peripheral region (PR) having a driving circuit (101) for displaying an image through the display region, and a sealine region (SLR) that surrounds the display region (DR) to define the display region and the peripheral region (PR). The first insulation layer (306) is formed over the transparent substrate (304), and the first insulation layer (306) has an opening window (301) in the sealine region (SLR). The pixel electrode (103) is formed on the first insulation layer (306) of the display region (DR). The bonding between a color filter substrate (401) and an array substrate (100a) is improved. Furthermore, liquid crystal material is completely filled into between the color filter substrate and the array substrate.

摘要翻译： 阵列基板（100a）包括透明基板（304），第一绝缘层（306）和像素电极（103）。 透明基板（304）包括显示图像的显示区域（DR），具有用于通过显示区域显示图像的驱动电路（101）的外围区域（PR）和围绕该图像的封闭区域（SLR） 显示区域（DR）以限定显示区域和外围区域（PR）。 第一绝缘层（306）形成在透明基板（304）上，第一绝缘层（306）在密封区域（SLR）中具有开口窗口（301）。 像素电极（103）形成在显示区域（DR）的第一绝缘层（306）上。 滤色器基板（401）和阵列基板（100a）之间的接合被改善。 此外，液晶材料完全填充在滤色器基板和阵列基板之间。

公开(公告)号：US20050020042A1

公开(公告)日：2005-01-27

申请号：US10780244

申请日：2004-02-17

申请人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

发明人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

摘要翻译： 形成具有金属栅电极的半导体器件的方法包括在半导体衬底上顺序地形成栅极绝缘体，栅极多晶硅层和金属栅极层。 金属栅极层和栅极多晶硅层被顺序地图案化以形成包括堆叠栅极多晶硅图案和金属栅极图案的栅极图案。 形成氧化阻挡层以覆盖金属 - 栅极图案的侧壁的至少一部分。

公开(公告)号：US08803865B2

公开(公告)日：2014-08-12

申请号：US13422109

申请日：2012-03-16

申请人： Sung-Hoon Lim ,  Man Hong Na ,  Young-Je Cho ,  Sung-Man Kim ,  Min-Chul Song ,  Soo Jung Chae ,  Eu Gene Lee

发明人： Sung-Hoon Lim ,  Man Hong Na ,  Young-Je Cho ,  Sung-Man Kim ,  Min-Chul Song ,  Soo Jung Chae ,  Eu Gene Lee

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G02F1/13454 ,  G02F1/1339 ,  G02F1/1345 ,  G09G3/3688 ,  G09G3/3696 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2300/08 ,  H01L21/77

摘要： A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

摘要翻译： 液晶显示器包括基板，多条信号线，栅极驱动器和密封剂。 基板包括显示区域和显示区域外的周边区域。 信号线与衬底集成并且包括时钟信号线。 栅极驱动器包括位于时钟信号线和显示区域之间的级。 该台与衬底集成，并被配置为向显示区域施加栅极电压。 密封剂分布在周边区域的一部分上。 密封剂分配的密封区域包括密封线，并且时钟信号线位于密封线内。 时钟信号线比其他信号线更远离舞台。

公开(公告)号：US08624820B2

公开(公告)日：2014-01-07

申请号：US11588495

申请日：2006-10-28

申请人： Sung-Man Kim ,  Bong-Jun Lee ,  Shin-Tack Kang

发明人： Sung-Man Kim ,  Bong-Jun Lee ,  Shin-Tack Kang

IPC分类号： G09G3/36 ,  G02F1/1343 ,  G02F1/1345

CPC分类号： G09G3/3659 ,  G02F1/134336 ,  G02F1/136286 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2320/0219 ,  G09G2320/0247

摘要： A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.

摘要翻译： 液晶显示器（LCD）包括基板; 第一和第二像素行，形成在基板上并且包括多个像素; 在所述基板上沿行方向延伸并与所述第一像素行连接的第一栅极线; 与所述第一像素列连接的在所述基板上的行方向上延伸的第二栅极线; 在所述基板上沿所述行方向延伸的第三栅极线，与所述第二像素行连接并且与所述第二栅极线相邻; 与所述第二像素列连接的在所述基板上沿行方向延伸的第四栅极线; 在基板上沿列方向延伸的多条数据线，其中，每两条像素都配置有数据线; 与第一和第四栅极线连接并将栅极信号施加到第一和第四栅极线的第一栅极驱动器; 以及与第二和第三栅极线连接并将栅极信号施加到第二和第三栅极线的第二栅极驱动器。

公开(公告)号：US08400412B2

公开(公告)日：2013-03-19

申请号：US12614377

申请日：2009-11-06

申请人： Sun-Kyu Joo ,  Ju-Hyeon Baek ,  Ji-Young Jeong ,  Sung-Man Kim ,  Myung-Sub Lee

发明人： Sun-Kyu Joo ,  Ju-Hyeon Baek ,  Ji-Young Jeong ,  Sung-Man Kim ,  Myung-Sub Lee

IPC分类号： G06F3/041

CPC分类号： G06F3/0418 ,  G02F1/13338 ,  G02F1/13394 ,  G02F1/136259 ,  G02F2001/13396 ,  G02F2201/508 ,  G06F3/0412 ,  Y10T29/49105

摘要： Provided are a display panel which can detect a touch position derived from a user's touch and can prevent erroneous touch position data from being generated even when an erroneous connection to a position sensing line is present due a processing deviation or a cell gap deviation, and a manufacturing method of the same. The display panel includes a first substrate, a first sensor pad that is formed on the first substrate, a second sensor pad that is spaced apart from the first sensor pad, a second substrate that is disposed to face the first substrate, a first sensor spacer that is formed on the second substrate to overlap the first sensor pad and protrudes toward the first substrate, a second sensor spacer that is formed on the second substrate to overlap the second sensor pad and protrudes toward the first substrate, and a sensor electrode that is formed on the first sensor spacer and the second sensor spacer to overlap the first sensor pad and the second sensor pad, wherein the second sensor spacer protrudes toward the first substrate more than the first sensor spacer does.

摘要翻译： 提供了一种显示面板，其可以检测从用户的触摸导出的触摸位置，并且即使当由于处理偏差或单元格间隙偏差而存在与位置感测线的错误连接时也可以防止错误的触摸位置数据，并且 制造方法相同。 显示面板包括第一基板，形成在第一基板上的第一传感器垫，与第一传感器垫间隔开的第二传感器垫，与第一基板相对设置的第二基板，第一传感器间隔件 形成在所述第二基板上以与所述第一传感器焊盘重叠并朝向所述第一基板突出的第二传感器间隔件，形成在所述第二基板上以与所述第二传感器焊盘重叠并朝向所述第一基板突出的第二传感器间隔件， 形成在所述第一传感器间隔物和所述第二传感器间隔物上以与所述第一传感器垫和所述第二传感器垫重叠，其中所述第二传感器间隔物比所述第一传感器间隔物更向第一基底突出。

公开(公告)号：US20120217514A1

公开(公告)日：2012-08-30

申请号：US13344268

申请日：2012-01-05

申请人： Sun-Kyu Joo ,  Ho-Kyoon Kwon ,  Sung-Man Kim

发明人： Sun-Kyu Joo ,  Ho-Kyoon Kwon ,  Sung-Man Kim

IPC分类号： H01L33/08 ,  H01L33/36

CPC分类号： G02F1/13394 ,  G02F1/136213 ,  G02F2001/134345 ,  H01L29/41733

摘要： A substrate includes a storage line, first and second gate lines and first and second pixel electrodes. The storage line extends along a first direction on the substrate. The first and second gate lines are substantially parallel with the storage line. The first pixel electrode is formed between the first gate line and the storage line. The second pixel electrode is formed between the second gate line and the storage line.

摘要翻译： 衬底包括存储线，第一和第二栅极线以及第一和第二像素电极。 存储线沿衬底上的第一方向延伸。 第一和第二栅极线基本上与存储线平行。 第一像素电极形成在第一栅极线和存储线之间。 第二像素电极形成在第二栅极线和存储线之间。

公开(公告)号：US07955908B2

公开(公告)日：2011-06-07

申请号：US11674457

申请日：2007-02-13

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L21/00

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US07920242B2

公开(公告)日：2011-04-05

申请号：US10565837

申请日：2004-06-11

申请人： Young-Goo Song ,  Hyang-Shik Kong ,  Sung-Man Kim

发明人： Young-Goo Song ,  Hyang-Shik Kong ,  Sung-Man Kim

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339 ,  G02F1/1341

摘要： An array substrate (100a) includes a transparent substrate (304), a first insulation layer (306) and a pixel electrode (103). The transparent substrate (304) includes a display region (DR) that displays an image, a peripheral region (PR) having a driving circuit (101) for displaying an image through the display region, and a sealine region (SLR) that surrounds the display region (DR) to define the display region and the peripheral region (PR). The first insulation layer (306) is formed over the transparent substrate (304), and the first insulation layer (306) has an opening window (301) in the sealine region (SLR). The pixel electrode (103) is formed on the first insulation layer (306) of the display region (DR). The bonding between a color filter substrate (401) and an array substrate (100a) is improved. Furthermore, liquid crystal material is completely filled into between the color filter substrate and the array substrate.

摘要翻译： 阵列基板（100a）包括透明基板（304），第一绝缘层（306）和像素电极（103）。 透明基板（304）包括显示图像的显示区域（DR），具有用于通过显示区域显示图像的驱动电路（101）的外围区域（PR）和围绕该图像的封闭区域（SLR） 显示区域（DR）以限定显示区域和外围区域（PR）。 第一绝缘层（306）形成在透明基板（304）上，第一绝缘层（306）在密封区域（SLR）中具有开口窗口（301）。 像素电极（103）形成在显示区域（DR）的第一绝缘层（306）上。 滤色器基板（401）和阵列基板（100a）之间的接合被改善。 此外，液晶材料完全填充在滤色器基板和阵列基板之间。