公开(公告)号：US10162641B2

公开(公告)日：2018-12-25

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/10

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US20170308141A1

公开(公告)日：2017-10-26

申请号：US15638407

申请日：2017-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui

IPC: G06F1/28 ,  G06F13/26 ,  G06F9/30

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

公开(公告)号：US20150019845A1

公开(公告)日：2015-01-15

申请号：US14326969

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30167

Abstract: The invention allows a processor to maintain a fixed instruction width regardless of the width of the constants needed. The constant extension solves the problem of having variable length opcodes to accommodate longer constants. The invention allows the architecture to have a fixed width, regardless of the width of the constants specified, which simplify instruction decoding. Constant widths can be variable and extend beyond the fixed processor instruction width.

Abstract translation: 本发明允许处理器维持固定的指令宽度，而与所需常数的宽度无关。 常数扩展解决了具有可变长度操作码以适应更长常数的问题。 本发明允许架构具有固定的宽度，而不管指定的常数的宽度，这简化了指令解码。 恒定宽度可以是可变的并且延伸超出固定的处理器指令宽度。

公开(公告)号：US20150019835A1

公开(公告)日：2015-01-15

申请号：US14327038

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885

Abstract: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.

Abstract translation: 矢量处理器的预测方法，通过使用单独的条件代码扩展来最大限度地减少大多数指令中嵌入谓词字段的使用。 专用谓词寄存器提供向量指令的精细粒度预测，其中谓词寄存器的每个位控制向量数据的8位。