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112 条记录 (耗时 0.043 秒)

    Image processing apparatus, image processing method, and computer-readable storage device
    92.
    发明授权
    Image processing apparatus, image processing method, and computer-readable storage device 有权
    图像处理装置，图像处理方法和计算机可读存储装置

    公开(公告)号：US09065968B2

    公开(公告)日：2015-06-23

    申请号：US13248460

    申请日：2011-09-29

    申请人： Takashi Kono ,  Yamato Kanda ,  Makoto Kitamura ,  Takehiro Matsuda ,  Masashi Hirota

    发明人： Takashi Kono ,  Yamato Kanda ,  Makoto Kitamura ,  Takehiro Matsuda ,  Masashi Hirota

    IPC分类号： H04N5/14 ,  G06T7/00

    CPC分类号： H04N5/142 ,  G06T7/13 ,  G06T7/181 ,  G06T2207/10068 ,  G06T2207/30028 ,  G06T2207/30092

    摘要： An image processing apparatus includes a contour-candidate-edge detecting unit that detects, as contour candidate edges, edges based on a gradient magnitude of each pixel in a target image; a contour-edge detecting unit that detect contour edges by performing thresholding on gradient magnitudes of the contour candidate edges; an interpolation-line generating unit that generates interpolation lines for connecting end points of respective end-point pairs based on gradients of pixel values between the end points while each of the end point pairs is made up of an end point of an identical contour edge as a connection base and an end point of a different contour edge as a connection destination; and a contour-edge interpolating unit that selects one of the interpolation lines based on the gradients of pixel values on the interpolation lines and interpolates a contour edge between the end points with the selected interpolation line.

    摘要翻译： 图像处理装置包括轮廓候选边缘检测单元，其基于目标图像中的每个像素的梯度大小来检测作为轮廓候选边缘的边缘; 轮廓边缘检测单元，其通过对所述轮廓候选边缘的梯度幅度进行阈值处理来检测轮廓边缘; 插补线生成单元，其基于端点对之间的像素值的梯度生成用于连接各端点对的端点的插补线，而每个端点对由相同轮廓边缘的端点组成， 连接基座和作为连接目的地的不同轮廓边缘的终点; 以及轮廓边缘内插单元，其基于所述插补线上的像素值的梯度选择所述插值线之一，并且利用所选择的插补线插值所述端点之间的轮廓边缘。

    Image processing apparatus, image processing method, and computer-readable recording medium
    94.
    发明授权
    Image processing apparatus, image processing method, and computer-readable recording medium 有权
    图像处理装置，图像处理方法和计算机可读记录介质

    公开(公告)号：US08897520B2

    公开(公告)日：2014-11-25

    申请号：US13210802

    申请日：2011-08-16

    申请人： Yamato Kanda ,  Makoto Kitamura ,  Takehiro Matsuda ,  Takashi Kono ,  Masashi Hirota

    发明人： Yamato Kanda ,  Makoto Kitamura ,  Takehiro Matsuda ,  Takashi Kono ,  Masashi Hirota

    IPC分类号： G06K9/00 ,  G06T7/00

    CPC分类号： G06T7/0012 ,  G06T2207/10024 ,  G06T2207/10068 ,  G06T2207/10152 ,  G06T2207/30028

    摘要： An image processing apparatus includes an approximate value calculating unit that calculates an approximate value that becomes consecutive inside an examination area for a pixel value of each pixel of the examination area based on the pixel value inside an image, a validity evaluating unit that evaluates whether the approximate value is valid on the pixel value, an area dividing unit that divides the examination area with the approximate value that is evaluated as being invalid, an examination area re-setting unit that sets each divided area obtained by the area dividing unit as a new examination area and controls a repetition of processing, and an abnormal portion detecting unit that detects an abnormal portion based on the pixel value inside the image and the approximate value that has been evaluated as being valid by the validity evaluating unit.

    摘要翻译： 图像处理装置包括近似值计算单元，其基于图像内的像素值计算在检查区域内对于检查区域的每个像素的像素值变得连续的近似值，有效性评估单元，其评估是否 近似值对像素值有效，区域划分单元，其将检查区域与被评估为无效的近似值分隔;检查区域重新设定单元，其将由区域划分单元获得的每个划分区域设置为新的 检查区域并控制重复处理;以及异常部分检测单元，其基于图像内的像素值和由有效性评估单元评估为有效的近似值来检测异常部分。

    Image processing apparatus, image processing method, and computer-readable recording medium
    97.
    发明授权
    Image processing apparatus, image processing method, and computer-readable recording medium 有权
    图像处理装置，图像处理方法和计算机可读记录介质

    公开(公告)号：US08457376B2

    公开(公告)日：2013-06-04

    申请号：US13104363

    申请日：2011-05-10

    申请人： Makoto Kitamura ,  Yamato Kanda ,  Takashi Kono ,  Masashi Hirota ,  Takehiro Matsuda

    发明人： Makoto Kitamura ,  Yamato Kanda ,  Takashi Kono ,  Masashi Hirota ,  Takehiro Matsuda

    IPC分类号： G06K9/00

    CPC分类号： G06T7/0012 ,  G06T7/90 ,  G06T2207/10016 ,  G06T2207/10068 ,  G06T2207/20021 ,  G06T2207/30092

    摘要： An image processing apparatus includes an identification criterion creating unit that creates an identification criterion so as to enable identification of specific regions in a target image to be processed that is selected in chronological order from among images constituting a set of time-series images; includes a feature data calculating unit that calculates the feature data of each segmented region in the target image to be processed; and includes a specific region identifying unit that, based on the feature data of each segmented region, identifies the specific regions in the target image to be processed by using the identification criterion. Moreover, the identification criterion creating unit creates the identification criterion based on the pieces of feature data of the specific regions identified in the images that have been already processed.

    摘要翻译： 图像处理装置包括：识别标准创建单元，其创建识别标准，以便能够识别从构成一组时间序列图像的图像中按时间顺序选择的要处理的目标图像中的特定区域; 包括特征数据计算单元，其计算要处理的目标图像中的每个分割区域的特征数据; 并且包括特定区域识别单元，其基于每个分割区域的特征数据，通过使用识别标准来识别要处理的目标图像中的特定区域。 此外，识别标准创建单元基于已经被处理的图像中识别的特定区域的特征数据的片段来创建识别标准。

    Nonvolatile semiconductor memory device having assist gate
    98.
    发明申请
    Nonvolatile semiconductor memory device having assist gate 失效
    具有辅助门的非易失性半导体存储器件

    公开(公告)号：US20060280022A1

    公开(公告)日：2006-12-14

    申请号：US11411938

    申请日：2006-04-27

    申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    IPC分类号： G11C8/00

    CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

    摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

    摘要翻译： 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

    Chip type capacitor, method for preparing the same and anode terminal used for preparing the same
    99.
    发明申请
    Chip type capacitor, method for preparing the same and anode terminal used for preparing the same 审中-公开
    片式电容器，其制备方法以及用于制备其的阳极端子

    公开(公告)号：US20050168921A1

    公开(公告)日：2005-08-04

    申请号：US11097316

    申请日：2005-04-04

    申请人： Mitsunori Sano ,  Takashi Kono

    发明人： Mitsunori Sano ,  Takashi Kono

    IPC分类号： H01G9/00 ,  H01G9/012 ,  H01G13/00

    CPC分类号： H01G9/012 ,  H01G2/02 ,  H01G4/236

    摘要： A chip type capacitor is disclosed which has improved bond strength between an anode lead wire and an anode terminal and enhanced reliability. A method for preparing the chip type capacitor and an anode terminal used in the preparation method are also disclosed. The chip type capacitor comprises: a solid electrolytic capacitor element including an element body having an anode body, a dielectric and a cathode body, and an anode lead wire partially extending from the anode body of the element body; and an anode terminal electrically connected to the anode lead wire, the anode lead wire having such a site that about 75% or more of a periphery of a section thereof in the direction substantially perpendicular to the extending direction of the anode lead wire is covered with solidified matter resulting from solidification of a melt, the anode terminal and the anode lead wire being bonded to each other by the solidified matter.

    摘要翻译： 公开了一种芯片型电容器，其具有改善的阳极引线和阳极端子之间的结合强度，并提高了可靠性。 还公开了制备方法中制备芯片型电容器和阳极端子的方法。 芯片型电容器包括：固体电解电容器元件，包括具有阳极体，电介质和阴极体的元件体和从元件体的阳极体部分延伸的阳极引线; 以及与阳极引线电连接的阳极端子，具有这样的位置的阳极引线被覆在与阳极引线的延伸方向大致垂直的方向上的部分的周边的大约75％以上的位置 由熔体固化而产生的固化物，阳极端子和阳极引线通过凝固物彼此接合。

    Semiconductor memory device with clock generating circuit
    100.
    发明授权
    Semiconductor memory device with clock generating circuit 失效
    具有时钟发生电路的半导体存储器件

    公开(公告)号：US06842396B2

    公开(公告)日：2005-01-11

    申请号：US10387503

    申请日：2003-03-14

    申请人： Takashi Kono

    发明人： Takashi Kono

    IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227

    摘要： A DLL clock control circuit determines whether or not an operating frequency is a low frequency satisfying a prescribed condition, based on signals received from a DLL circuit and a READ control circuit. When the DLL clock control circuit determines that the operating frequency is a low frequency, the DLL clock control circuit outputs a DLL clock received from the DLL circuit if a first signal to be activated in response to a READ command is activated, while when determining that an operating frequency is not a low frequency, outputting a DLL clock received from the DLL circuit if a second signal to be activated in response to an ACT command is activated. As a result, a semiconductor memory device can guarantees a data output operating in data reading and can reduce power consumption during active standby.

    摘要翻译： DLL时钟控制电路基于从DLL电路和READ控制电路接收的信号来判定工作频率是否为满足规定条件的低频。 当DLL时钟控制电路确定操作频率是低频时，如果响应于READ命令被激活的第一信号被激活，则DLL时钟控制电路输出从DLL电路接收的DLL时钟，而当确定 如果激活响应于ACT命令被激活的第二信号，则工作频率不是低频，输出从DLL电路接收的DLL时钟。 结果，半导体存储器件可以保证在数据读取中操作的数据输出并且可以在主动待机期间降低功耗。