公开(公告)号：US10707213B2

公开(公告)日：2020-07-07

申请号：US16178521

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Hung Wang ,  En-Chiuan Liou ,  Chien-Hao Chen ,  Sho-Shen Lee ,  Yi-Ting Chen ,  Jhao-Hao Lee

IPC: H01L21/311 ,  H01L27/108 ,  H01L21/027 ,  H01L21/033

Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

公开(公告)号：US20200035782A1

公开(公告)日：2020-01-30

申请号：US16116859

申请日：2018-08-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  En-Chiuan Liou ,  Yu-Cheng Tung ,  Wei-Lun Hsu ,  Yu-Hsiang Hung ,  Ming-Te Wei ,  Le-Tien Jung

IPC: H01L49/02 ,  H01L27/02 ,  H01L29/94 ,  H01G4/01

Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.

公开(公告)号：US20190229024A1

公开(公告)日：2019-07-25

申请号：US16368795

申请日：2019-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/66 ,  G03F7/20 ,  H01L23/544

CPC classification number: H01L22/12 ,  G03F7/70633 ,  G03F7/70683 ,  H01L22/30 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

公开(公告)号：US10347716B2

公开(公告)日：2019-07-09

申请号：US15786611

申请日：2017-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/283

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

公开(公告)号：US10340381B2

公开(公告)日：2019-07-02

申请号：US16180033

申请日：2018-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: The present invention provides a method for fabricating a semiconductor structure, the method at least comprises: firstly, a substrate is provided, a dielectric layer is formed on the substrate, a gate conductive layer and two spacers are formed and disposed in the dielectric layer, wherein the two spacers are respectively disposed on both sides of the gate conductive layer, next, parts of the gate conductive layer are removed, and parts of the two spacers are removed, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and afterwards, a stress cap layer is then formed, overlying the gate conductive layer and the two spacers, wherein parts of the stress cap layer is located right above the two spacers.

公开(公告)号：US10332877B2

公开(公告)日：2019-06-25

申请号：US15242591

申请日：2016-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

公开(公告)号：US10283616B2

公开(公告)日：2019-05-07

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US20190081150A1

公开(公告)日：2019-03-14

申请号：US16178580

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/49 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/7843

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US10205005B1

公开(公告)日：2019-02-12

申请号：US15691717

申请日：2017-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/24 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/08

Abstract: A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

公开(公告)号：US10170369B1

公开(公告)日：2019-01-01

申请号：US15806295

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.