Analysis and detection of soft hang responsiveness program errors
    91.
    发明授权
    Analysis and detection of soft hang responsiveness program errors 失效
    分析和检测软挂起响应程序错误

    公开(公告)号:US08166464B2

    公开(公告)日:2012-04-24

    申请号:US12163806

    申请日:2008-06-27

    IPC分类号: G06F9/44 G06F11/00

    摘要: Analyzing and detecting soft hang program errors may lead to suggestions for either curing the programming errors at runtime or refactoring the source code. For instance, responsive function invocation patterns and blocking function invocation patterns may be used to detect soft hang program errors in a source code file. Deductive database rules may be compiled from the responsive and blocking function invocation patterns to find matching function invocations in a call graph.

    摘要翻译: 分析和检测软挂起程序错误可能会导致在运行时修复编程错误或重构源代码的建议。 例如,响应函数调用模式和阻塞函数调用模式可用于检测源代码文件中的软挂起程序错误。 演绎数据库规则可以从响应和阻止函数调用模式中编译,以在调用图中找到匹配的函数调用。

    Dynamic Circuit Adjustment
    92.
    发明申请
    Dynamic Circuit Adjustment 有权
    动态电路调整

    公开(公告)号:US20120093507A1

    公开(公告)日:2012-04-19

    申请号:US12905147

    申请日:2010-10-15

    IPC分类号: H04B10/20

    摘要: A system and method are provided for dynamically reconfiguring an optical circuit between a first node and a second node of a communication network. The system and method may include establishing a scheduling window for receiving a plurality of optical traffic demands, classifying the plurality of optical traffic demands into at least a set of bandwidth adjustable demands and a set of fixed bandwidth demands, provisioning a first set of provisioned wavelengths from the plurality of wavelengths to carry the set of fixed bandwidth demands during the scheduling window, allocating the bandwidth remaining on the first set of provisioned wavelengths to the set of bandwidth adjustable demands, and if necessary, provisioning a second set of provisioned wavelengths from the plurality of wavelengths to carry the bandwidth required by the set of bandwidth adjustable demands that could not be allocated to the first set of provisioned wavelengths.

    摘要翻译: 提供了一种用于在通信网络的第一节点和第二节点之间动态重新配置光电路的系统和方法。 该系统和方法可以包括建立用于接收多个光学业务​​需求的调度窗口,将多个光学业务​​需求分类为至少一组带宽可调节需求和一组固定带宽需求,提供第一组供应波长 从所述多个波长在所述调度窗口期间携带所述固定带宽需求集合,将所述第一组所设置的波长上剩余的带宽分配给所述带宽可调节需求集合,并且如果需要,从所述多个波长中提供第二组所提供的波长 多个波长以承载不能分配给第一组所配置的波长的一组带宽可调节需求所需的带宽。

    Determining disjoint paths with an optimized number of regenerators
    93.
    发明授权
    Determining disjoint paths with an optimized number of regenerators 有权
    确定具有优化数量的再生器的不相交路径

    公开(公告)号:US08144626B2

    公开(公告)日:2012-03-27

    申请号:US12494397

    申请日:2009-06-30

    IPC分类号: H04L12/28

    摘要: According to particular embodiments, determining disjoint paths includes receiving a graph representing a network comprising nodes and links. The graph is transformed such that the number of intermediate nodes of a path indicates the number of regenerators for the path. A set of seed paths from a source node to a destination node of the transformed graph is generated. For each seed path, a shortest path from the source node to the destination node is determined to yield one or more pairs of disjoint paths from the source node to the destination node. An optimized pair of disjoint paths is selected, where the optimized pair of disjoint paths has an optimized number of regenerators.

    摘要翻译: 根据特定实施例,确定不相交路径包括接收表示包括节点和链路的网络的图。 图形被变换,使得路径的中间节点的数量表示路径的再生器的数量。 生成从变换图的源节点到目标节点的一组种子路径。 对于每个种子路径,确定从源节点到目的地节点的最短路径以产生从源节点到目的地节点的一对或多对不相交路径。 选择优化的一对不相交路径,其中优化的一对不相交路径具有优化的再生器数量。

    SOI MOS DEVICE HAVING A SOURCE/BODY OHMIC CONTACT AND MANUFACTURING METHOD THEREOF
    94.
    发明申请
    SOI MOS DEVICE HAVING A SOURCE/BODY OHMIC CONTACT AND MANUFACTURING METHOD THEREOF 有权
    具有源/体OHMIC接触的SOI MOS器件及其制造方法

    公开(公告)号:US20120009741A1

    公开(公告)日:2012-01-12

    申请号:US13131126

    申请日:2010-09-07

    IPC分类号: H01L21/336

    摘要: The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology.

    摘要翻译: 本发明公开了一种具有源/体欧姆接触的SOI MOS器件的制造方法。 该制造方法包括以下步骤:首先产生栅极区域,然后进行高剂量源和漏极掺杂以形成轻掺杂的N型源极区域和轻掺杂的N型漏极区域; 形成围绕所述栅极区域的绝缘间隔物; 通过在N型Si源极区域的位置处具有开口的掩模在倾斜方向上进行大倾斜重掺杂P离子注入,并且将P离子注入到N型Si源极区域和N型漏极区域之间的空间中,以 形成重掺杂P型区; 最后在N型Si源区上形成金属层,然后通过热处理使金属层与下面残留的Si材料之间的反应形成硅化物。 在通过本发明的方法制备的器件中,在硅化物和附近的重掺杂P型区域之间形成欧姆接触,以释放积累在SOI MOS器件的体区中的空穴并消除浮体效应 其中。 此外,本发明的器件还具有以下优点,例如有限的芯片面积,简化的制造工艺和与传统CMOS技术的很好的兼容性。

    DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF
    95.
    发明申请
    DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF 有权
    DRAM电池利用浮动体的效果及其制造方法

    公开(公告)号:US20110292723A1

    公开(公告)日:2011-12-01

    申请号:US12937257

    申请日:2010-07-14

    摘要: The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

    摘要翻译: 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的P型半导体区域,设置在P型半导体区域上的N型半导体区域,设置在N型半导体区域上的栅极区域和围绕P型半导体的电隔离区域 区域和N型半导体区域。 将浮体效应的二极管作为存储节点。 通过带之间的隧道效应,电子聚集在浮体中,其被定义为第一存储状态; 通过PN结的正向偏压,电子从浮体发出,或者将空穴注入到浮动体中,其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元,其具有低功耗,制造工艺简单,并且与常规CMOS和常规逻辑电路制造工艺兼容。

    HYBRID MATERIAL INVERSION MODE GAA CMOSFET
    96.
    发明申请
    HYBRID MATERIAL INVERSION MODE GAA CMOSFET 失效
    混合材料反相模式GAA CMOSFET

    公开(公告)号:US20110254101A1

    公开(公告)日:2011-10-20

    申请号:US12810694

    申请日:2010-02-11

    IPC分类号: H01L27/092

    摘要: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

    摘要翻译: Ge和Si混合材料反转模式GAA(Gate-All-Around)CMOSFET包括具有第一沟道的PMOS区域,具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下,电流流过整个圆柱形通道,以实现高载流子迁移率,降低低频噪声,防止多晶硅栅极耗尽和短沟道效应,并增加器件的阈值电压。

    SYSTEMS AND METHODS FOR DETERMINING PROTECTION PATHS IN A MULTI-DOMAIN NETWORK
    97.
    发明申请
    SYSTEMS AND METHODS FOR DETERMINING PROTECTION PATHS IN A MULTI-DOMAIN NETWORK 有权
    用于确定多域网络中的保护程序的系统和方法

    公开(公告)号:US20110243030A1

    公开(公告)日:2011-10-06

    申请号:US12751599

    申请日:2010-03-31

    IPC分类号: H04L12/28

    摘要: Systems and methods for determining multiple paths in a multi-domain network are provided. In some embodiment, a method for determining multiple paths in a network is provided. The method may include determining a first path between a source node and a destination node and determining a second path disjoint from the first path. In some embodiments, to determine the second path includes determining which ingress nodes are available in a domain that includes the destination node, where the available ingress nodes are not part of the first path, and implementing a disjoint path algorithm for each of the available ingress nodes. To determine the first path includes implementing forward path calculations.

    摘要翻译: 提供了用于确定多域网络中的多个路径的系统和方法。 在一些实施例中,提供了一种用于确定网络中的多个路径的方法。 该方法可以包括确定源节点和目的地节点之间的第一路径并确定与第一路径不相交的第二路径。 在一些实施例中,为了确定第二路径包括确定哪些入口节点在包括目的地节点的域中是可用的,其中可用入口节点不是第一路径的一部分,并且为每个可用入口实现不相交路径算法 节点。 确定第一条路径包括实现前向路径计算。

    Minimizing Interconnections In A Multi-Shelf Switching System
    98.
    发明申请
    Minimizing Interconnections In A Multi-Shelf Switching System 有权
    最小化多层交换系统中的互连

    公开(公告)号:US20110167183A1

    公开(公告)日:2011-07-07

    申请号:US12683504

    申请日:2010-01-07

    IPC分类号: G06F13/14 G06F13/00

    CPC分类号: H04L47/10 H04L41/12

    摘要: In certain embodiments, minimizing interconnections in a multi-shelf switching system includes receiving a map describing the switching system, where the switching system comprises shelves and input/output (I/O) points. The map is transformed to yield a graph comprising nodes and edges. A node represents an I/O point, and a node weight represents a number of interface cards of the I/O point represented by the node. An edge between a node pair represents traffic demand between the I/O points represented by the node pair, and an edge weight represents the amount of the traffic demand represented by the edge. The graph is partitioned to yield a groups that minimize interconnection traffic among the shelves, where each group represents a shelf of the multi-shelf switching system.

    摘要翻译: 在某些实施例中,最小化多货架交换系统中的互连包括接收描述交换系统的映射,其中交换系统包括货架和输入/输出(I / O)点。 该图被变换以产生包括节点和边的图。 节点表示I / O点,节点权重表示由节点表示的I / O点的接口卡数量。 节点对之间的边缘表示由节点对表示的I / O点之间的业务需求,边缘权重表示由边缘表示的业务量需求量。 该图被分割以产生使架之间的互连流量最小化的组,其中每个组表示多货架交换系统的货架。