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107 条记录 (耗时 0.015 秒)

    DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF 有权
    DRAM电池利用浮动体的效果及其制造方法

    公开(公告)号：US20110292723A1

    公开(公告)日：2011-12-01

    申请号：US12937257

    申请日：2010-07-14

    申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

    发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

    IPC分类号： G11C11/38 ,  H01L21/336 ,  H01L29/772

    CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

    摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

    摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的P型半导体区域，设置在P型半导体区域上的N型半导体区域，设置在N型半导体区域上的栅极区域和围绕P型半导体的电隔离区域 区域和N型半导体区域。 将浮体效应的二极管作为存储节点。 通过带之间的隧道效应，电子聚集在浮体中，其被定义为第一存储状态; 通过PN结的正向偏压，电子从浮体发出，或者将空穴注入到浮动体中，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

    Two terminal silicon based negative differential resistance device
    2.
    发明授权
    Two terminal silicon based negative differential resistance device 有权
    两端硅基负差分电阻器件

    公开(公告)号：US07016224B2

    公开(公告)日：2006-03-21

    申请号：US10884576

    申请日：2004-07-02

    申请人： Tsu-Jae King

    发明人： Tsu-Jae King

    IPC分类号： G11C11/38

    CPC分类号： G11C11/412 ,  G11C2211/5614

    摘要： A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.

    摘要翻译： 公开了一种双端子硅基负差动电阻（NDR）元件，以实现用于所选应用的一种NDR二极管。 两端子器件基于具有修改的沟道掺杂分布的三端NDR功能FET，其中栅极连接到漏极。 该器件可以通过常规CMOS处理与其他NDR和非NDR元件（包括具有NDR功能的FET）进行集成。 还公开了使用这种NDR两端元件和NDR三端的存储单元。

    Static memory cell with load circuit using a tunnel diode
    3.
    发明授权
    Static memory cell with load circuit using a tunnel diode 失效
    使用隧道二极管的负载电路的静态存储单元

    公开(公告)号：US6104631A

    公开(公告)日：2000-08-15

    申请号：US991966

    申请日：1997-12-17

    申请人： El-Badawy Amien El-Sharawy ,  Majid M. Hashemi

    发明人： El-Badawy Amien El-Sharawy ,  Majid M. Hashemi

    IPC分类号： G11C11/38 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/34

    CPC分类号： G11C11/412

    摘要： A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.

    摘要翻译： 静态RAM存储单元（30）使用交叉耦合增强模式，N沟道MOS驱动晶体管（36）形成双稳态触发器。 负载电路（34）耦合在驱动晶体管（36）和Vcc的I / O端口（40）之间。 对于每个驱动晶体管（36），负载电路包括耗尽模式N沟道MOS负载晶体管（54）和正向偏置隧道二极管（32）。 负载晶体管（54）的漏极和栅极耦合在隧道二极管（32）的阳极和阴极之间，使得隧道二极管（32）的正向电压（Vf）控制负载的Vgs转移曲线（56） 晶体管。

    Tunnel diode with several permanent switching states
    4.
    发明授权
    Tunnel diode with several permanent switching states 失效
    具有多个永久开关状态的隧道二极管

    公开(公告)号：US5541422A

    公开(公告)日：1996-07-30

    申请号：US353844

    申请日：1994-12-12

    申请人： Ronald M. Wolf ,  Paulus W. M. Blom ,  Marcellinus P. C. M. Krijn

    发明人： Ronald M. Wolf ,  Paulus W. M. Blom ,  Marcellinus P. C. M. Krijn

    IPC分类号： G11C11/22 ,  G11C11/38 ,  G11C11/56 ,  H01L27/115 ,  H01L29/08 ,  H01L29/51 ,  H01L29/88 ,  H01L45/00 ,  H01L29/06

    CPC分类号： H01L29/88 ,  G11C11/22 ,  G11C11/38 ,  G11C11/5657 ,  H01L27/115 ,  H01L29/0895 ,  H01L29/51 ,  H01L45/00

    摘要： The invention relates to a tunnel diode provided with two metallically conducting electrodes (1, 2) with an insulating dielectric (3) in between, which forms a barrier with a barrier level for electrons and which has a thickness such that electrons can tunnel through the barrier from the one to the other electrode. Such a tunnel diode has the disadvantage that it has no memory. In many applications it is desirable for the tunnel diode to hold a certain switching state, such as open/closed. According to the invention, the tunnel diode is characterized in that the dielectric (3) comprises a layer of a material which is ferroelectric at room temperature with a remanent polarization which influences the barrier level. It is achieved thereby that the tunnel diode has various switching states in dependence on the remanent polarization of the dielectric (3). The switching state is maintained until the polarization of the dielectric (3) changes.

    摘要翻译： 本发明涉及一种隧道二极管，其设置有两个在其间具有绝缘电介质（3）的金属导电电极（1,2），其形成具有用于电子的势垒级别的势垒，并且具有使得电子能穿过 从一个到另一个电极的屏障。 这种隧道二极管的缺点是它没有存储器。 在许多应用中，期望隧道二极管保持一定的开关状态，例如开/关。 根据本发明，隧道二极管的特征在于，电介质（3）包括在室温下铁电的材料层，其具有影响势垒层的剩余极化。 因此，隧道二极管根据电介质（3）的剩余极化具有各种开关状态。 保持开关状态，直到电介质（3）的极化发生变化。