公开(公告)号：US5184327A

公开(公告)日：1993-02-02

申请号：US727218

申请日：1991-07-09

申请人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C29/30

CPC分类号： G11C29/30

摘要： In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15 20). The output line (L) is provided with plural junction points (n1 to nn) to which detection results from the detection circuits (14, 15 20) are separately applied. Dividing transistors (T1 to Tn) are provided between the junction points (n1 to nn). During testing, the word lines (WL1 to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4) connected to the selected word line are outputted at the corresponding junction points (n1 to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.

摘要翻译： 在半导体存储器件的存储单元阵列中，与多个列对应地提供多个检测电路（14,15,20）。 输出线（L）与检测电路（14,1520）共同设置。 输出线（L）具有分别施加有检测电路（14,15,20）的检测结果的多个连接点（n1〜nn）。 分接晶体管（T1至Tn）设置在连接点（n1至nn）之间。 在测试期间，顺序选择字线（WL1至WLn）。 连接到所选字线的存储单元（MC1至MC4）的测试结果分别在对应的连接点（n1至nn）输出。 同时，与所选字线对应的分割晶体管不导通，剩余的分割晶体管导通。 结果，输出线（L）在非导电晶体管的一部分被分成两部分。 检测输出到输出线（L）的分割部分的检测结果，并且求出检测结果在各分割部分发生变化的部分。

公开(公告)号：US5088063A

公开(公告)日：1992-02-11

申请号：US532338

申请日：1990-06-05

申请人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/30 ,  G11C29/34

CPC分类号： G11C29/30

摘要： In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15, 20). The output line (L) is provided with plural junction points (nl to nn) to which detection results from the detection circuits (14, 15, 20) are separately applied. Dividing transistors (Tl to Tn) are provided between the junction points (nl to nn). During testing, the work lines (WLl to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4 ) connected to the selected word line are outputted at the corresponding junction points (nl to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.

摘要翻译： 在半导体存储器件的存储单元阵列中，与多个列对应地提供多个检测电路（14,15,20）。 输出线（L）与检测电路（14,15,20）共同设置。 输出线（L）设置有分别施加有来自检测电路（14,15,20）的检测结果的多个结点（n1至nn）。 分接晶体管（T1至Tn）设置在连接点（nl至nn）之间。 在测试期间，依次选择工作线（WL1至WLn）。 连接到所选字线的存储单元（MC1至MC4）的测试结果分别在对应的连接点（nl至nn）输出。 同时，与所选字线对应的分割晶体管不导通，剩余的分割晶体管导通。 结果，输出线（L）在非导电晶体管的一部分被分成两部分。 检测输出到输出线（L）的分割部分的检测结果，并且求出检测结果在各分割部分发生变化的部分。

公开(公告)号：US5060230A

公开(公告)日：1991-10-22

申请号：US400899

申请日：1989-08-30

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC分类号： G06F11/267 ,  G11C29/00 ,  G11C29/12 ,  G11C29/34

CPC分类号： G11C29/78 ,  G11C29/12 ,  G11C29/34 ,  G06F11/267

摘要： An apparatus for parallel testing of a semiconductor memory with arbitrary data patterns and capable of being integrated on the memory chip. The semiconductor memory test device in a preferred embodiment is compatible with hierarchical data bus lines including an input/output line pair (I/O, I/O), a plurality of sub-input/output line pairs (SIO1SIO1; SIO2, SIO2) and a plurality of bit line pairs (BL1, BL1; BL6, BL6). A plurality of comparators (50) and a plurality of registers (60) are provided corresponding to a plurality of sub-input/output line pairs (SIO1, SIO2; SIO2, SIO2). The plurality of registers (50) which also functions as intermediated output amplifiers can hold random data applied through the input/output line pair (I/O, I/O). The plurality of comparators (60) is provided to determine whether or not data read out onto a plurality of sub-input/output line pairs (SIO1, SIO1; SIO2, SIO2) from a row of memory cells (MC1, MC2) corresponding to a single word line (WL) match respective data held in the plurality of registers (60).

摘要翻译： 一种用于并行测试具有任意数据模式并能够集成在存储器芯片上的半导体存储器的装置。 优选实施例中的半导体存储器测试装置与包括输入/​​输出线对（I / O，I / O），多个子输入/输出线对（SIO1 + L，SIO1; SIO2，SIO2）和多个位线对（BL1，BL1; BL6，BL6）。 对应于多个子输入/输出线对（SIO1，SIO2; SIO2，SIO2）提供多个比较器（50）和多个寄存器（60）。 也可以用作中间输出放大器的多个寄存器（50）可以保存通过输入/输出线对（I / O，I / O）施加的随机数据。 多个比较器（60）被提供以确定从对应于存储单元（MC1，MC2）的一行的多个子输入/输出线对（SIO1，SIO1; SIO2，SIO2） 单个字线（WL）匹配保存在多个寄存器（60）中的相应数据。

公开(公告)号：US4980310A

公开(公告)日：1990-12-25

申请号：US412742

申请日：1989-09-26

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10829 ,  Y10S257/911

摘要： A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the central portion of the trench so as to correspond to the memory cells for two bits, and a field oxide film formed at the center of the trench on the bottom and on the side walls for separating the capacitors and elements.

公开(公告)号：US4972380A

公开(公告)日：1990-11-20

申请号：US206416

申请日：1988-06-14

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： H01L21/82 ,  G11C5/06 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C29/00 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03M7/00 ,  H03M7/22

CPC分类号： G11C8/12 ,  G11C5/066 ,  G11C29/006

摘要： An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

摘要翻译： 用于功能块的地址解码电路包括彼此串行连接的分支部分，其中当选择信号被施加到第一个时，根据地址信号的第一位信息在两个输出部分之一上输出选择信号 阶段分支部分。 根据选择信号，施加选择信号的第二级输出部分响应于地址信号的第二位信息，在两个输出部分之一上输出选择信号。 此后，根据从前一级施加的选择信号，第三至最后级的每个分支部分响应于第三位的相应内容输出地址信号的最后一位的两个输出部分之一上的选择信号。 通过该选择信号，选择作为功能块部分的存储单元并被激活。

公开(公告)号：US4890261A

公开(公告)日：1989-12-26

申请号：US206417

申请日：1988-06-14

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C7/00 ,  G06F12/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401

CPC分类号： G11C8/12 ,  G11C7/1006

摘要： A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is grouped to form a fixed recirculation path. The word length can be varied by modifying stored data in the shift register without changing its recirculation path.

摘要翻译： 半导体存储器的字长可变电路包括与存储单元阵列的行或列对应地设置的移位寄存器。 移位寄存器的第一级的输入连接到最后级的输出端，移位寄存器的区域被分组以形成固定的再循环路径。 可以通过修改移位寄存器中存储的数据而不改变其再循环路径来改变字长。

公开(公告)号：US4887136A

公开(公告)日：1989-12-12

申请号：US110462

申请日：1987-10-20

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10829 ,  Y10S257/911

摘要： A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the central portion of the trench so as to correspond to the memory cells for two bits, and a field oxide film formed at the center of the trench on the bottom and on the side walls for separating the capacitors and elements.

摘要翻译： 一种动态半导体存储器件，包括具有一个沟槽的衬底，该沟槽包括用于存储器单元电容两位的两个电容器，以及用于读取，写入和存储由电荷表示的信息的晶体管的两个元件，其对称地布置在沟槽的中心部分处 对应于两位的存储单元，以及形成在底部和侧壁上的沟槽中心的场氧化膜，用于分离电容器和元件。

公开(公告)号：US4849938A

公开(公告)日：1989-07-18

申请号：US76401

申请日：1987-07-22

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/844

摘要： In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. A line decoder is responsive to the input address for selecting one of the lines of the normal memory cells, and is inactivated by the output of the comparator when the input address is found to coincide with the programmed address. An input address to the line decoder is applied before the same input address is applied to the comparator.

摘要翻译： 在具有主存储单元的行（行或列）和响应于缺陷行的地址而替代缺陷行的备用存储单元的行的冗余配置的半导体存储器件中，比较器将输入到 存储器件，其中已经编程的缺陷线的地址，并且当发现输入地址与编程地址一致时，备用线选择器选择备用线。 行解码器响应于输入地址以选择正常存储器单元的一行，并且当发现输入地址与编程地址一致时，比较器的输出被非激活。 在将相同的输入地址应用于比较器之前，施加到线路解码器的输入地址。

公开(公告)号：US4833653A

公开(公告)日：1989-05-23

申请号：US94642

申请日：1987-09-09

申请人： Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： A DRAM of a partially activating system, in which, in an active cycle, sense amplifiers (91a, 91b) are inactivated and the potential on each pair of bit lines (BLA1, BLA1, BLA2, BLA2) is equalized early in the active cycle only for a subarray to be accessed while the potential is not equalized and the sense amplifiers are kept to be activated for a subarray not to be accessed. At the time of an inactive cycle, all the sense amplifiers (91a, 91b) are activated, and the bit lines (BLA1, BLA1, BLA2, BLA2) in the memory cell array are at an "H" or "L" level depending on information read out in the previous active cycle.

摘要翻译： 部分激活系统的DRAM，其中在有效周期中，感测放大器（91a，91b）被去激活，并且每对位线（BLA1，＆amp; B，BA2，＆amp; B＆B）上的电位在 只有当电位不均衡时才对待访问的子阵列进行有效周期，并且为不被访问的子阵列保持激活读出放大器。 在非活动周期时，所有读出放大器（91a，91b）都被激活，并且存储单元阵列中的位线（BLA1，＆amp; B，B，BLA2，＆UPBALB和B）处于“H”或“L” 取决于在上一个活动周期中读出的信息。

公开(公告)号：US4833645A

公开(公告)日：1989-05-23

申请号：US929367

申请日：1986-11-12

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1085 ,  H01L27/10805

摘要： In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.

摘要翻译： 在本发明的半导体存储装置中，在p型半导体基板（1）上形成与位线（12）连接的漏型扩散区域（9a），形成型源扩散区域（9b） 与n型漏极区域（9a）具有规定的间隔。 在p型硅基板（1）上，以高杂质密度的p型扩散区域（16a）和高杂质浓度的p型扩散区域（16b）以与n型漏极扩散接触的方式形成 区域（9a）和n型源极扩散区域（9b），但不在n沟道MOS晶体管（18）的沟道区域中。 因此，可以在不改变传输门晶体管的阈值电压的情况下降低α粒子产生的电荷。