公开(公告)号：US07245616B1

公开(公告)日：2007-07-17

申请号：US10103436

申请日：2002-03-20

Applicant: Nathan Elnathan ,  Alexander Joffe ,  Ilan Pardo

Inventor： Nathan Elnathan ,  Alexander Joffe ,  Ilan Pardo

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/3072

Abstract: Tasks are dynamically allocated to process packets. In particular, packets of data to be processed are assigned a packet identification. The packet identification includes a lane and a packet sequence number. The term “lane” as used herein refers to a port number and a direction (i.e. ingress or egress), such as Port 3 Egress. A set of resources (e.g., registers and memory buffers) are associated with each lane. The task is allowed to access resources associated with the lane. In some embodiments, a task may change the port that it services and use the resources associated with that port.

Abstract translation: 动态分配任务以处理数据包。 特别地，要处理的数据分组被分配一个分组标识。 分组标识包括通道和分组序列号。 本文所用的术语“通道”是指端口号和方向（即入口或出口），例如端口3出口。 一组资源（例如，寄存器和存储器缓冲器）与每个通道相关联。 该任务被允许访问与该通道相关联的资源。 在一些实施例中，任务可以改变其服务的端口并使用与该端口相关联的资源。

公开(公告)号：US07221652B1

公开(公告)日：2007-05-22

申请号：US10378480

申请日：2003-03-03

Applicant: Sushil Kumar Singh ,  Kenneth Yi Yun ,  Jianfeng Shi ,  Eli James Aubrey Fernald ,  Kirk Alvin Miller ,  Prayag Bhanubhai Patel ,  Ayoob Eusoof Dooply ,  George Beshara Bendak

Inventor： Sushil Kumar Singh ,  Kenneth Yi Yun ,  Jianfeng Shi ,  Eli James Aubrey Fernald ,  Kirk Alvin Miller ,  Prayag Bhanubhai Patel ,  Ayoob Eusoof Dooply ,  George Beshara Bendak

IPC: G01R31/08

CPC classification number: H04L12/5601 ,  H04L49/106 ,  H04L2012/5665 ,  H04L2012/5675

Abstract: A system and method are provided for tolerating data line faults in a packet communications network. The method comprises: serially transmitting information packets from at least one traffic manager (TM); at a switch fabric, accepting information packets at a plurality of ingress ports, the information packets addressing destination port card egress ports; selectively connecting port card ingress ports to port card egress ports; serially supplying information packets from a plurality of port card egress ports; sensing a connection fault between the switch fabric and the TM; and, in response to sensing the fault, reselecting connections between the switch fabric port card ports and the TM. Some aspects comprise: an ingress memory subsystem (iMS) receiving cells on an ingress port exceeding an error threshold. Then, reselecting connections between the port card ports and the TM includes the iMS sending a message to the iTM identifying the faulty ingress connection.

Abstract translation: 提供了一种用于容忍分组通信网络中的数据线路故障的系统和方法。 该方法包括：从至少一个业务管理器（TM）串行发送信息分组; 在交换结构中，接收多个入口端口的信息分组，所述信息分组寻址目的地端口卡出口; 将端口卡入口端口选择性连接到端口卡出口端口; 从多个端口卡出口端口串行提供信息包; 感测交换结构与TM之间的连接故障; 并且响应于感测到故障，重新选择交换结构端口卡端口和TM之间的连接。 一些方面包括：入口存储器子系统（iMS）在入口端口上接收超过错误阈值的小区。 然后，重新选择端口卡端口和TM之间的连接包括iMS向iTM发送消息，以识别错误的入口连接。

公开(公告)号：US20070110059A1

公开(公告)日：2007-05-17

申请号：US11648920

申请日：2007-01-03

Applicant: Jeffrey Spires ,  Ravi Subrahmanyan

Inventor： Jeffrey Spires ,  Ravi Subrahmanyan

IPC: H04L12/56

CPC classification number: H04J3/076

Abstract: A system and modulation method are provided for reducing jitter in the mapping of information into Synchronous Payload Envelopes (SPEs), in a data tributary mapping system. The method comprises buffering data from a plurality of tributaries, and generating buffer-fill information responsive to the buffered data being written and read. The buffer-fill information is filtered, producing rate control information. The rate control information is modulated, and the modulated rate control information is used in controlling the mapping of buffered tributaries into a SPE. The rate control information can be modulated with periodic signals, such as a sine or square wave, and pseudorandom signals with an average value of about zero.

Abstract translation: 提供了一种系统和调制方法，用于在数据支路映射系统中减少信息映射到同步有效载荷包络（SPE）中的抖动。 该方法包括缓冲来自多个支路的数据，以及响应于正被写入和读取的缓冲数据产生缓冲器填充信息。 缓冲填充信息被过滤，产生速率控制信息。 速率控制信息被调制，并且调制速率控制信息用于控制缓冲支路到SPE的映射。 速率控制信息可以用诸如正弦波或方波的周期信号和平均值约为零的伪随机信号进行调制。

公开(公告)号：US07212523B2

公开(公告)日：2007-05-01

申请号：US10401282

申请日：2003-03-27

Applicant: Narendra K. Bansal ,  Gary Martin

Inventor： Narendra K. Bansal ,  Gary Martin

IPC: H04L12/50

CPC classification number: H04Q11/0421 ,  H04Q3/68 ,  H04Q2213/13076 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  H04Q2213/13341

Abstract: An architecture for a high bandwidth digital cross-connect switching system that is internally non-blocking, has a simpler layout, and employs a reduced number of logic gates. The high bandwidth digital cross-connect switching architecture comprises a Time Division Multiplexing (TDM) cross-connect including M space/time switches. Each space/time switch includes an input bus, an output bus, N×W Flip-Flops (FFs) for storing input data, W N-by-N switches for sorting the data according to predetermined cross-connection requirements, and N×W FFs for storing output data, in which “N” corresponds to the number of input ports and the number of output ports in the N-by-N switch, and “W” corresponds to the width of each data word. Each N-by-N switch includes N×W N-to-1 selectors, and the M space/time switches include N×W M-to-1 selectors, thereby allowing an effective N×M-to-1 selection to be performed on the data words.

Abstract translation: 用于内部非阻塞的高带宽数字交叉连接交换系统的架构具有更简单的布局，并且采用减少数量的逻辑门。 高带宽数字交叉连接交换架构包括包括M个空间/时间交换机的时分复用（TDM）交叉连接。 每个空间/时间开关包括输入总线，输出总线，用于存储输入数据的NxW触发器（FF），用于根据预定的交叉连接要求对数据进行排序的N N个N开关，以及用于存储的NxWFF 输出数据，其中“N”对应于N-N开关中的输入端口数量和输出端口数量，“W”对应于每个数据字的宽度。 每个N-N开关包括N×W个N-1选择器，并且M个空间/时间开关包括N×W M-1选择器，从而允许对数据字进行有效的N×M-1选择。

公开(公告)号：US07188225B1

公开(公告)日：2007-03-06

申请号：US10900998

申请日：2004-07-28

Applicant: Christophe Therene ,  Paul R. Stonelake ,  Alex Ga Hing Tang ,  Richard L. Harris

Inventor： Christophe Therene ,  Paul R. Stonelake ,  Alex Ga Hing Tang ,  Richard L. Harris

IPC: G06F12/00

CPC classification number: G06F11/1441 ,  G06F12/0804 ,  G06F12/0866

Abstract: A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When a disk drive power-on-reset event is detected, the disk array may be efficiently restored to an operational state by re-executing or “replaying” a set of write commands that are cached within the disk array controller. The invention is also applicable to single-disk-drive storage systems.

Abstract translation: 磁盘阵列控制器可靠地检测可能导致存储在其高速缓存中的未提交写入数据的磁盘驱动器的磁盘驱动器上电复位事件丢失此类数据。 用于检测上电复位事件的方法包括以ATA安全模式操作磁盘驱动器，其中磁盘驱动器的上电复位将导致驱动器进入数据传输命令被中止的锁定状态; 以及随着时间的推移跟踪磁盘驱动器的功率循环计数属性。 当检测到磁盘驱动器上电复位事件时，可以通过重新执行或重播在盘阵列控制器中缓存的一组写入命令来将磁盘阵列有效地还原到操作状态。 本发明也适用于单盘驱动器存储系统。

公开(公告)号：US07162401B1

公开(公告)日：2007-01-09

申请号：US10402817

申请日：2003-03-28

Applicant: Robert Emil Abeles

Inventor： Robert Emil Abeles

IPC: G06F17/50 ,  G06G7/62

CPC classification number: G06F17/5022

Abstract: Whenever a resource being modeled is accessed, an indication about the access is stored in a number of memory locations of a corresponding number of applications that are interested in monitoring the resource. The memory locations (also called “monitoring memory locations”) are individually identified for each application when allocating a location in main memory. At this time, a pointer to the monitoring memory location is supplied to the application and also added to a group of pointers of locations to be updated when accessing the resource. In addition, in certain embodiments, a bit is allocated within a bitmap for each monitoring memory location for any given application. Such a bit is set at the time of updating the corresponding monitoring memory location and cleared when the application reads the monitoring memory location. Just checking the bitmap as a whole can inform an application if there is any change in any monitoring memory locations of that application. Moreover, the application may use individual bits of the bitmap to identify (and cycle through) only those monitoring memory locations that have changed. Update of monitoring memory locations may be implemented via overloading of operators that access each resource.

Abstract translation: 每当访问被建模的资源时，关于访问的指示被存储在对监视资源感兴趣的相应数量的应用程序的多个存储器位置中。 当在主存储器中分配位置时，为每个应用程序分别识别存储器位置（也称为“监视存储器位置”）。 此时，指向监视存储器位置的指针被提供给应用，并且还被添加到访问资源时要更新的位置的一组指针。 此外，在某些实施例中，在针对任何给定应用的每个监视存储器位置的位图内分配一个位。 在更新相应的监视存储器位置时设置这样的位，并且当应用读取监视存储器位置时被清除。 只需检查位图作为一个整体，可以通知应用程序，如果该应用程序的任何监视内存位置有任何更改。 此外，应用程序可以使用位图的各个位来识别（并循环）只有那些已经改变的监视存储器位置。 可以通过访问每个资源的运营商的超载来实现对监视存储器位置的更新。

公开(公告)号：US07130367B1

公开(公告)日：2006-10-31

申请号：US10120599

申请日：2002-04-09

Applicant: Wei Fu ,  Joseph J. Balardeta ,  James Corona

Inventor： Wei Fu ,  Joseph J. Balardeta ,  James Corona

IPC: H03D3/24

CPC classification number: H03L7/0812

Abstract: A digital delay lock loop (DLL) circuit for receiving parallel data and clock signals, deserializing the high speed parallel data to low speed data, and for improving setup and hold times. A DLL circuit for an N-bit datapath, includes a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals. The DLL circuit further includes N data DLLs, each being configured to adjust a delay of a data signal to substantially center the eye opening of the data signal on the clock signal pulse.

Abstract translation: 一种用于接收并行数据和时钟信号的数字延迟锁定环路（DLL）电路，将高速并行数据反序列化为低速数据，并改善设置和保持时间。 一种用于N位数据路径的DLL电路，包括被配置为在每个N个数据信号的眼睛开口内提供时钟信号脉冲的时钟DLL。 DLL电路还包括N个数据DLL，每个数据DLL被配置为调整数据信号的延迟，以使时钟信号脉冲上的数据信号的眼图开度基本居中。

公开(公告)号：US07103131B1

公开(公告)日：2006-09-05

申请号：US10218804

申请日：2002-08-14

Applicant: Thomas Clark Byran ,  Hongwen Lu ,  Wei Fu

Inventor： Thomas Clark Byran ,  Hongwen Lu ,  Wei Fu

IPC: H03D3/24

CPC classification number: H03L7/091 ,  H04L7/033

Abstract: A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q1; latching the divided data with a second half-rate clock, the inverse of the first clock, creating Q2; latching Q1 with the second clock, creating Q3; latching Q2 with the first clock, creating Q4; XORing Q1 and Q2 to create phase signals; and, XORing Q3 and Q4 to create reference signals, corresponding to the phase signals. In some aspects of the method, dividing the stream of data by two introduces a processing delay into the divided data. Then, the method further comprises: in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks; delaying the received stream of binary data; and, using the first and second clocks to sample the delayed binary data.

Abstract translation: 提供了半速率相位检测的系统和方法。 该方法包括：接收二进制数据; 将数据除以2; 用第一半速率时钟锁存分割的数据，创建Q 1; 用第二个半速率时钟锁存分割的数据，即第一个时钟的倒数，产生Q 2; 用第二个时钟锁定Q 1，创建Q 3; 用第一个时钟锁定Q 2，创建Q 4; XORing Q 1和Q 2产生相位信号; 并且，XORing Q 3和Q 4产生对应于相位信号的参考信号。 在该方法的某些方面，将数据流除以2将处理延迟引入分割数据。 然后，该方法还包括：响应于相位和参考信号，锁相压控振荡器以产生第一和第二时钟; 延迟所接收的二进制数据流; 并且使用第一和第二时钟对延迟的二进制数据进行采样。

公开(公告)号：US07073001B1

公开(公告)日：2006-07-04

申请号：US10116177

申请日：2002-04-03

Applicant: Nick Kucharewski ,  Yair Hadas

Inventor： Nick Kucharewski ,  Yair Hadas

IPC: G06F13/42

CPC classification number: G06F13/4291

Abstract: A method of synchronizing or initiating channel lock in a serial loop formed by an initializing transceiver and subject transceivers disclosed. Should a transceiver in the serial loop detect that its receiving serial channel is desynchronized, it sends an unlock signal to the next transceiver in the loop. The unlock signal guarantees that the next transceiver's receiving serial channel will be desynchronized. Only the initializing transceiver may initiate a channel lock sequence.

Abstract translation: 一种在由初始化收发器和主体收发器形成的串行环路中同步或启动信道锁定的方法。 如果串行回路中的收发器检测到其接收串行通道不同步，则它会向循环中的下一个收发器发送解锁信号。 解锁信号保证下一个收发器的接收串行通道将被同步。 只有初始化收发器可以启动信道锁定序列。

公开(公告)号：US07072361B1

公开(公告)日：2006-07-04

申请号：US10094259

申请日：2002-03-08

Applicant: Andrew Mark Player

Inventor： Andrew Mark Player

IPC: H04J3/16 ,  H04J3/22

CPC classification number: H04J3/14 ,  H04J3/1611

Abstract: A system and method are provided for transporting backward information in a digital wrapper format network of connected simplex devices. The system comprises a first simplex processor receiving downstream messages with overhead bytes. The first simplex processor selectively replaces overhead bytes with calculated overhead bytes and supplies the calculated overhead bytes. The system further comprises a buffer receiving the calculated overhead bytes from the first simplex processor and supplying the calculated overhead bytes. A second simplex processor accepts the calculated overhead bytes from the buffer and supplies an upstream message including the calculated overhead bytes. The first simplex processor receives messages in a frame format with an overhead section, drops the overhead section, and selectively reads backward message monitor bytes in the dropped overhead section to determine if upstream communication nodes are receiving transmitted messages.

Abstract translation: 提供了一种用于在连接的单工装置的数字包装格式网络中传送反向信息的系统和方法。 该系统包括接收具有开销字节的下行消息的第一单工处理器。 第一个单工处理器用计算出的开销字节选择性地替换开销字节，并提供计算的开销字节。 该系统还包括缓冲器，其从第一单工处理器接收所计算的开销字节并提供所计算的开销字节。 第二个单工处理器接受来自缓冲区的计算开销字节，并提供包括计算的开销字节的上游消息。 第一单工处理器以帧格式接收具有开销部分的消息，丢弃开销部分，并且选择性地读取丢弃的开销部分中的反向消息监视字节，以确定上游通信节点是否正在接收发送的消息。