公开(公告)号：US07130367B1

公开(公告)日：2006-10-31

申请号：US10120599

申请日：2002-04-09

申请人： Wei Fu ,  Joseph J. Balardeta ,  James Corona

发明人： Wei Fu ,  Joseph J. Balardeta ,  James Corona

IPC分类号： H03D3/24

CPC分类号： H03L7/0812

摘要： A digital delay lock loop (DLL) circuit for receiving parallel data and clock signals, deserializing the high speed parallel data to low speed data, and for improving setup and hold times. A DLL circuit for an N-bit datapath, includes a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals. The DLL circuit further includes N data DLLs, each being configured to adjust a delay of a data signal to substantially center the eye opening of the data signal on the clock signal pulse.

摘要翻译： 一种用于接收并行数据和时钟信号的数字延迟锁定环路（DLL）电路，将高速并行数据反序列化为低速数据，并改善设置和保持时间。 一种用于N位数据路径的DLL电路，包括被配置为在每个N个数据信号的眼睛开口内提供时钟信号脉冲的时钟DLL。 DLL电路还包括N个数据DLL，每个数据DLL被配置为调整数据信号的延迟，以使时钟信号脉冲上的数据信号的眼图开度基本居中。

公开(公告)号：US07139348B1

公开(公告)日：2006-11-21

申请号：US10120598

申请日：2002-04-09

申请人： Wei Fu ,  Joseph J. Balardeta

发明人： Wei Fu ,  Joseph J. Balardeta

IPC分类号： H03D3/24 ,  H03L7/06 ,  G06F1/12

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0805 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/033

摘要： A distributed clock circuit for clocking high speed data at various different physical locations on a chip while improving setup and hold times. The clock circuit includes a master delay lock loop (DLL) circuit configured to lock a global clock signal with a first data signal, and output a clock delay control signal when the global clock signal is locked. The clock circuit further includes one or more slave DLL circuits, coupled to receive the clock delay control signal to lock a local clock signal with a local data signal, wherein the local clock signal is based on the global clock signal.

摘要翻译： 一种分布式时钟电路，用于在提高设置和保持时间的同时在芯片上的各种不同物理位置对高速数据进行计时。 时钟电路包括被配置为利用第一数据信号锁定全局时钟信号的主延迟锁定环（DLL）电路，并且当全局时钟信号被锁定时输出时钟延迟控制信号。 时钟电路还包括一个或多个从属DLL电路，被耦合以接收时钟延迟控制信号以用本地数据信号锁定本地时钟信号，其中本地时钟信号基于全局时钟信号。

公开(公告)号：US07057418B1

公开(公告)日：2006-06-06

申请号：US10823060

申请日：2004-04-13

申请人： Wei Fu ,  Sudhaker Reddy Anumula ,  Hongwen Lu ,  Joseph J. Balardeta

发明人： Wei Fu ,  Sudhaker Reddy Anumula ,  Hongwen Lu ,  Joseph J. Balardeta

IPC分类号： G01R25/00

CPC分类号： H03D13/003 ,  G01R25/005

摘要： A high-speed, half rate phase detector provides an effective solution to the problem of XOR gate response to the minimum width signal precursors (Q1 and Q2) of a phase signal that indicates a phase difference between a data signal and a clock signal by combining the precursor signals in a multiplexer and combining the multiplexed signal with the data signal in an XOR gate. This affords the transition information in the transitions of the precursor signals, which is significant of phase difference, without requiring the XOR gate to respond to the minimum widths of those pulses.

摘要翻译： 高速，半速率相位检测器提供了对相位信号的最小宽度信号前导（Q 1和Q 2）的异或门响应的问题的有效解决方案，该相位信号表示数据信号和时钟信号之间的相位差 通过组合多路复用器中的前驱信号并将复用的信号与数据信号组合在异或门中。 这提供了前驱信号的转变中的转换信息，其相位差是显着的，而不需要XOR门对这些脉冲的最小宽度做出响应。

公开(公告)号：US06545524B1

公开(公告)日：2003-04-08

申请号：US10085613

申请日：2002-02-26

申请人： Sudhaker Reddy Anumula ,  Wei Fu ,  Joseph J. Balardeta ,  Paul Vanderbilt ,  Allen C. Merrill

发明人： Sudhaker Reddy Anumula ,  Wei Fu ,  Joseph J. Balardeta ,  Paul Vanderbilt ,  Allen C. Merrill

IPC分类号： H03K1762

CPC分类号： H03L7/087 ,  H03L7/0891

摘要： A configurable multiplexing circuit and arrangement suited for phase locked loop applications. The multiplexing circuit includes an EX-OR element, a multiplexer element and a summer element. Each element is configured for receiving a particular type of detection signal output, as an input for one of multiple selectable multiplexing operations. The multiplexing circuit further includes a selection signal input, coupled to the EX-OR element, the multiplexer element and the summer element, for receiving a selection signal that enables one or more of the EX-OR element, the multiplexer element, and the summer element. Non-enabled elements are powered down to eliminate jitter and performance penalties.

摘要翻译： 适用于锁相环应用的可配置复用电路和布置。 复用电路包括EX-OR元件，复用器元件和加法元件。 每个元件被配置为接收特定类型的检测信号输出，作为多个可选复用操作之一的输入。 复用电路还包括耦合到EX-OR元件的选择信号输入，多路复用器元件和加法元件，用于接收使EX-OR元件，多路复用器元件和夏天中的一个或多个的选择信号 元件。 未使能的元件掉电，以消除抖动和性能损失。

公开(公告)号：US06469574B1

公开(公告)日：2002-10-22

申请号：US09771241

申请日：2001-01-26

申请人： Mehmet M. Eker ,  Wei Fu ,  Joseph J. Balardeta

发明人： Mehmet M. Eker ,  Wei Fu ,  Joseph J. Balardeta

IPC分类号： H03B100

CPC分类号： H03H21/0001

摘要： A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

摘要翻译： 已经提供了一种用于可选择地将输入信号均衡到集成电路（IC）的系统和方法，以补偿传输过程中的劣化。 可选择均衡电路包括并行均衡和非均衡部分。 当均衡部分被接合时，谐振元件修改电路阻抗以向电路传递函数添加零。 当非均衡功能被接合时，均衡部分脱离而不降低栅极电容，并且输入信号在传递函数中被处理而没有零。

公开(公告)号：US06822483B1

公开(公告)日：2004-11-23

申请号：US10121013

申请日：2002-04-09

申请人： Wei Fu ,  Joseph J. Balardeta

发明人： Wei Fu ,  Joseph J. Balardeta

IPC分类号： G01R2500

CPC分类号： G01R25/005

摘要： A bang-bang phase detector circuit for use in a delay lock loop is disclosed. The phase detector includes a data signal line, a clock signal line, and a delay cell having an input coupled to the data signal line. The phase detector further includes a first double flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line, and a second double flip-flop having a data input coupled to an output of the delay cell and a clock input coupled to the clock signal line. A NOR circuit has a first input coupled to an output of the first double flip-flop and a second input coupled to an output of the second double flip-flop. The phase detector provides a lag output signal line coupled to an output of the NOR circuit, and a lead output signal line coupled to the output of the second double flip-flop.

摘要翻译： 公开了一种用于延迟锁定环路的爆轰相位检测器电路。 相位检测器包括数据信号线，时钟信号线和具有耦合到数据信号线的输入的延迟单元。 相位检测器还包括具有耦合到数据信号线的数据输入和耦合到时钟信号线的时钟输入的第一双触发器，以及具有耦合到延迟输出的数据输入的第二双触发器 单元和连接到时钟信号线的时钟输入。 NOR电路具有耦合到第一双触发器的输出的第一输入和耦合到第二双触发器的输出的第二输入。 相位检测器提供耦合到NOR电路的输出的延迟输出信号线和耦合到第二双触发器的输出的引出输出信号线。

公开(公告)号：US06744293B1

公开(公告)日：2004-06-01

申请号：US10120576

申请日：2002-04-09

申请人： Wei Fu ,  Joseph J. Balardeta

发明人： Wei Fu ,  Joseph J. Balardeta

IPC分类号： H03L706

CPC分类号： G06F1/10 ,  H03L7/0814 ,  H03L7/089

摘要： A circuit and method for de-skewing a global clock tree is disclosed. A circuit uses a digital delay lock loop having an incoming clock input, a local reference clock input, and a clock output providing an output clock signal. The delay lock loop receives an incoming clock signal and aligns it with a local reference clock signal, where the incoming clock signal is a skewed version of the local reference clock signal. The circuit further includes a clock tree for receiving the output clock signal and outputting a global clock signal when the delay lock loop is in lock mode. The output clock signal of the global clock tree represents a phase lock between an incoming clock signal on the incoming clock input and a local reference clock signal input on the local reference clock input.

摘要翻译： 公开了一种用于去偏斜全局时钟树的电路和方法。 电路使用具有输入时钟输入，本地参考时钟输入和提供输出时钟信号的时钟输出的数字延迟锁定环路。 延迟锁定环接收输入时钟信号并将其与本地参考时钟信号对齐，其中输入时钟信号是本地参考时钟信号的偏移版本。 电路还包括时钟树，用于在延迟锁定环处于锁定模式时接收输出时钟信号并输出​​全局时钟信号。 全局时钟树的输出时钟信号表示输入时钟输入端的输入时钟信号与本地参考时钟输入端输入的本地参考时钟信号之间的相位锁定。

公开(公告)号：US06642781B1

公开(公告)日：2003-11-04

申请号：US10236761

申请日：2002-09-06

申请人： Mehmet M. Eker ,  Wei Fu ,  Joseph J. Balardeta

发明人： Mehmet M. Eker ,  Wei Fu ,  Joseph J. Balardeta

IPC分类号： H03B100

CPC分类号： H03H21/0001

摘要： A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

公开(公告)号：US06566967B1

公开(公告)日：2003-05-20

申请号：US10085458

申请日：2002-02-26

申请人： Sudhaker Reddy Anumula ,  Joseph J. Balardeta ,  Wei Fu ,  Paul Vanderbilt ,  Mehmet Mustafa Eker

发明人： Sudhaker Reddy Anumula ,  Joseph J. Balardeta ,  Wei Fu ,  Paul Vanderbilt ,  Mehmet Mustafa Eker

IPC分类号： H03L700

CPC分类号： H03L7/18 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/107 ,  H03L7/113 ,  H03L7/14

摘要： A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.

摘要翻译： 具有多个检测元件的可配置PLL架构。 可配置PLL电路包括用于提供第一差分信号的第一检测器，用于提供第二差分信号的第二检测器，用于提供第三差分信号的第三检测器，以及用于使第一，第二和第 第三检测器。 PLL电路还包括多路复用器，用于从相应的使能检测器接收至少一个差分信号，并提供多路复用的差分信号输出。 在操作中，选择操作模式，并且启用一个或多个检测器以使用一个或多个输入参考信号进行操作。 使能的检测器的输出由多路复用器接收以完成所选择的操作模式的操作。

公开(公告)号：US08294501B1

公开(公告)日：2012-10-23

申请号：US13035331

申请日：2011-02-25

申请人： Christopher Thomas ,  Yanggao Qiu ,  Junling Zang ,  Wei Fu

发明人： Christopher Thomas ,  Yanggao Qiu ,  Junling Zang ,  Wei Fu

IPC分类号： H03H11/16

CPC分类号： H03L7/081 ,  H03L7/099 ,  H03L7/197

摘要： Systems and methods are disclosed for improving the accuracy of phase spacing of multiphase clocks. In one example, method includes receiving a reference clock having a first frequency and sampling the reference clock with a plurality of multiphase clocks having a second frequency to generate a plurality of samples. The second frequency is a non-integer multiple of the first frequency. The method also includes detecting transitions of the reference clock occurring between the samples generated from a plurality of pairs of the multiphase clocks and counting the transitions to generate a transition count for each pair of the multiphase clocks. The method also includes summing a set of the transition counts to generate a measured phase for a first multiphase clock, calculating a reference phase for the first multiphase clock, and generating a phase skew value for the first multiphase clock based on the measured phase and the reference phase.

摘要翻译： 公开了用于提高多相时钟相位精度的系统和方法。 在一个示例中，方法包括接收具有第一频率的参考时钟并且用具有第二频率的多个多相时钟采样参考时钟以产生多个采样。 第二频率是第一频率的非整数倍。 该方法还包括检测在从多对多相时钟产生的样本之间发生的参考时钟的转变，并对转换进行计数，以产生每对多相时钟的转换计数。 该方法还包括对一组转换计数求和以产生第一多相时钟的测量相位，计算第一多相时钟的参考相位，以及基于测量相位和第一多相时钟产生第一多相时钟的相位偏移值 参考阶段。