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129 条记录 (耗时 0.017 秒)

    Method and apparatus for gals system
    99.
    发明授权
    Method and apparatus for gals system 有权
    gals系统的方法和装置

    公开(公告)号：US09490817B1

    公开(公告)日：2016-11-08

    申请号：US13777500

    申请日：2013-02-26

    申请人： Marvell Israel (M.I.S.L) Ltd.

    发明人： Eitan Rosen

    IPC分类号： G01R31/02 ,  H03L7/00

    CPC分类号： H03L7/00 ,  G01R31/3016 ,  G01R31/31725 ,  H03K3/0315 ,  H03K5/135 ,  H03K7/00 ,  H03L7/07 ,  H03L7/0996

    摘要： Aspects of the disclosure provide a system. The system includes a first functional circuit, a first clock generator, a second functional circuit, and a second clock generator. The first functional circuit is configured to be operative in response to a first clock signal. The first clock generator is configured to generate the first clock signal with a first clock cycle being a function of a first number of first inversion delays. The second functional circuit is configured to be operative in response to a second clock signal. The second clock generator is configured to generate the second clock signal with a second clock cycle being a function of a second number of second inversion delays. In an embodiment, the first inversion delays are correlated to switching delays in the first functional circuit, and the second inversion delays are correlated to switching delays in the second functional circuit.

    摘要翻译： 本公开的方面提供了一种系统。 该系统包括第一功能电路，第一时钟发生器，第二功能电路和第二时钟发生器。 第一功能电路被配置为响应于第一时钟信号而工作。 第一时钟发生器被配置为产生第一时钟信号，第一时钟周期是第一数量的第一反相延迟的函数。 第二功能电路被配置为响应于第二时钟信号而工作。 第二时钟发生器被配置为产生第二时钟信号，第二时钟周期是第二数量的第二反相延迟的函数。 在一个实施例中，第一反相延迟与第一功能电路中的开关延迟相关，并且第二反相延迟与第二功能电路中的开关延迟相关。

    Modulation through differentially delayed clocks
    100.
    发明授权
    Modulation through differentially delayed clocks 有权
    通过差分延迟时钟进行调制

    公开(公告)号：US09166577B2

    公开(公告)日：2015-10-20

    申请号：US14167972

    申请日：2014-01-29

    申请人： QUALCOMM Incorporated

    发明人： Niranjan Anand Talwalkar ,  Sanjay Kasturia

    IPC分类号： H03K7/06 ,  H03K5/13 ,  H03K3/017 ,  H03K7/00

    CPC分类号： H03K5/133 ,  H03C3/403 ,  H03F1/0294 ,  H03F3/2178 ,  H03F3/24 ,  H03K3/017 ,  H03K7/00

    摘要： A clock modulator can include two configurable delay units and can receive a baseband signal and a clock signal. The two configurable delay units can generate two delayed clock signals, each with different delay amounts. The delay amounts can be based on the baseband signal. The delayed clock signals can be combined to generate a modulated clock signal. A quadrature modulated clock signal can be generated when a first clock modulator receives a first baseband signal and a first clock signal and a second clock modulator receives a second baseband signal and a second clock signal. The first clock signal can be a ninety-degree phase shifted version of the second clock signal. The modulated clock signal from the first clock modulator can be combined with the modulated clock signal from the second clock modulator to generate the quadrature modulated clock signal.

    摘要翻译： 时钟调制器可以包括两个可配置的延迟单元，并且可以接收基带信号和时钟信号。 两个可配置的延迟单元可以产生两个延迟时钟信号，每个具有不同的延迟量。 延迟量可以基于基带信号。 延迟的时钟信号可以被组合以产生调制的时钟信号。 当第一时钟调制器接收第一基带信号和第一时钟信号并且第二时钟调制器接收到第二基带信号和第二时钟信号时，可以产生正交调制时钟信号。 第一个时钟信号可以是第二个时钟信号的九十度相移版本。 来自第一时钟调制器的调制时钟信号可以与来自第二时钟调制器的调制时钟信号组合以产生正交调制时钟信号。