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    High-speed module, device and method for decoding a concatenated code
    92.
    发明申请
    High-speed module, device and method for decoding a concatenated code 失效
    用于解码级联代码的高速模块，设备和方法

    公开(公告)号：US20040054954A1

    公开(公告)日：2004-03-18

    申请号：US10416484

    申请日：2003-09-15

    发明人： Patrick Adde ,  Ramesh Pyndiah

    IPC分类号： H03M013/00

    CPC分类号： H03M13/6577 ,  H03M13/2963 ,  H03M13/6566

    摘要： The invention concerns a module for decoding a concatenated code, corresponding at least to two elementary codes C1 and C2, using storage means (81, 83, 90, 111, 113) wherein are stored samples of data to be decoded, comprising at least two elementary decoders (821, 822, . . . 82m) of at least one of the elementary codes, the elementary decoders associated with one of the elementary codes simultaneously processing, in parallel separate code words contained in the storage means.

    摘要翻译： 本发明涉及一种用于使用存储装置（81,83,90,111,113）对应于至少两个基本代码C1和C2的级联码进行解码的模块，其中存储要解码的数据样本，包括至少两个 所述基本代码中的至少一个的基本解码器（821,822，...，82m）与所述存储装置中包含的并行分离的代码字同时处理与所述基本代码之一相关联的基本解码器。

    Data readout device and data readout method
    94.
    发明申请
    Data readout device and data readout method 失效
    数据读出装置和数据读出方式

    公开(公告)号：US20030131305A1

    公开(公告)日：2003-07-10

    申请号：US10339548

    申请日：2003-01-09

    申请人： FUJITSU LIMITED

    发明人： Masakazu Taguchi ,  Akihiro Itakura

    IPC分类号： H03M013/00

    CPC分类号： H03M13/6343 ,  H03M13/15 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/41 ,  H03M13/6577

    摘要： A data readout device generates decoded data based on a decided data bit decided by performing a hard-decision on likelihood data, wherein the likelihood data is generated in accordance with an iterative decoding method corresponding to a turbo-coding process. The iterative decoding process is performed on a sampled value obtained by sampling a signal read out from a magneto-optical disk at a predetermined sampling period. The data readout device is made up of a reliability determination part and an error correcting decoder. The reliability determination part detects whether each obtained data bit was obtained from likelihood data within a predetermined range defined with respect to a histogram of log likelihood ratios. When it is detected that a data bit was obtained by a hard-decision on likelihood data within the predetermined range, the data bit is regarded as being obtained by a hard-decision whose reliability is not sufficient. In this way, the error correcting decoder can perform ECC-based decoding operations including loss-correction processes depending on respective reliability-determination results that distinguish reliabilities among respective data bits. Thus, the accuracy of decoded data is increased. The data transfer rate of transferring decoded data when reading out of the MO medium is also improved to the utmost.

    摘要翻译： 数据读出装置基于通过对似然数进行硬判定而决定的决定数据比特生成解码数据，其中，根据对应于turbo编码处理的迭代解码方法生成似然数据。 对通过在预定采样周期对从磁光盘读出的信号采样而获得的采样值执行迭代解码处理。 数据读出装置由可靠性判定部和纠错解码器构成。 可靠性确定部分检测每个获得的数据位是否从关于对数似然比的直方图定义的预定范围内的似然数据获得。 当检测到通过在预定范围内的似然数据的硬判决获得数据位时，数据位被认为是通过可靠性不足的硬判决获得的。 以这种方式，错误校正解码器可以根据区分各个数据位之间的可靠性的各个可靠性确定结果，执行包括损失校正处理的基于ECC的解码操作。 因此，解码数据的精度增加。 在读取MO介质时传送解码数据的数据传输速率也得到最大限度的提高。

    Implementation of a turbo decoder
    95.
    发明申请
    Implementation of a turbo decoder 失效
    turbo解码器的实现

    公开(公告)号：US20030014711A1

    公开(公告)日：2003-01-16

    申请号：US09905568

    申请日：2001-07-12

    发明人： Warm Shaw Yuan

    IPC分类号： H03M013/03

    CPC分类号： H03M13/658 ,  H03M13/2975 ,  H03M13/2981 ,  H03M13/2984 ,  H03M13/3911 ,  H03M13/6577 ,  H03M13/6586

    摘要： A method for computing the function log(ex1nullex2) or ln(ex1nullex2) for a first argument value x1 and a second argument value x2 includes generating a table having a first data field and a second data field. The first data field includes N entries of table index values selected from a range of nullx1-x2null argument values and scaled by a scaling factor. The second data field includes N entries of computed table values computed based on the equation log(1nullenullnullx1-x2null) or ln(1nullenullx1-x2null) for each of the nullx1-x2null argument values selected for the table index values. The computed table values are also scaled by the same scaling factor.

    摘要翻译： 用于计算第一参数值x1和第二自变量值x2的函数日志（ex1 + ex2）或ln（ex1 + ex2）的方法包括生成具有第一数据字段和第二数据字段的表。 第一数据字段包括从| x1-x2 |的范围中选择的表索引值的N个条目 参数值并按比例缩放。 第二数据字段包括对于| x1-x2 |中的每一个，基于等式log（1 + e- | x1-x2 |）或ln（1 + e-x1-x2 |）计算的计算表值的N个条目。 为表索引值选择的参数值。 计算的表值也按相同的缩放因子缩放。

    Turbo decoder with multiple scale selections
    96.
    发明申请
    Turbo decoder with multiple scale selections 有权
    具有多尺度选择的Turbo解码器

    公开(公告)号：US20030007577A1

    公开(公告)日：2003-01-09

    申请号：US09893046

    申请日：2001-06-27

    发明人： Da-shan Shiu ,  Rajesh Sundaresan

    IPC分类号： H03D001/00

    CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/3707 ,  H03M13/3776 ,  H03M13/3911 ,  H03M13/6337 ,  H03M13/6577 ,  H03M13/658

    摘要： Techniques to improve the performance of a Turbo decoder when scale information for the bits in a code segment to be decoded is not known. A number of hypotheses are formed for the code segment, with each hypothesis corresponding to a particular set of one or more values for a set of one or more parameters used for decoding the code segment. For the MAP decoding scheme, these parameters may be for the sequence of scaling factors used to scale the bits prior to decoding and/or a scale used to evaluate a (e.g., min*) function for the MAP decoding. The code segment is decoded based on the MAP decoding scheme and in accordance with each hypothesis. The quality of the decoded result for each hypothesis is determined based on one or more performance metrics. The decoded bits for the best hypothesis are provided as the Turbo decoder output.

    摘要翻译： 当解码的码段中的位的缩放信息不为人知时，提高Turbo解码器的性能的技术。 为代码段形成多个假设，其中每个假设对应于用于解码代码段的一个或多个参数的集合的一个或多个值的特定集合。 对于MAP解码方案，这些参数可以用于在解码之前用于缩放比特的缩放因子序列和/或用于评估用于MAP解码的（例如，min *）功能的比例。 根据MAP解码方案并根据每个假设对代码段进行解码。 基于一个或多个性能度量来确定每个假设的解码结果的质量。 提供最佳假设的解码位作为Turbo解码器输出。

    Method and apparatus for turbo-code decoding a convolution encoded data frame using symbol-by-symbol traceback and HR-SOVA
    97.
    发明授权
    Method and apparatus for turbo-code decoding a convolution encoded data frame using symbol-by-symbol traceback and HR-SOVA 失效
    用符号追溯和HR-SOVA对卷积编码数据帧进行turbo码解码的方法和装置

    公开(公告)号：US06487694B1

    公开(公告)日：2002-11-26

    申请号：US09467732

    申请日：1999-12-20

    申请人： Raminder Singh Bajwa

    发明人： Raminder Singh Bajwa

    IPC分类号： H03M1329

    CPC分类号： H03M13/4146 ,  H03M13/2957 ,  H03M13/6505 ,  H03M13/6577 ,  H03M13/6591

    摘要： The apparatus includes a first SOVA decoder that generates a first path reliability value from a channel value, a parity symbol and a first a priori likelihood value. A first decorrelation unit generates a first extrinsic symbol reliability value by decorrelating the channel value and the first a priori likelihood value from the path reliability value. A first symbol reliability saturation unit saturates the first extrinsic symbol reliability value to generate a first saturated extrinsic symbol reliability value. A first interleaver interleaves the first saturated extrinsic symbol reliability value to generate a second a priori likelihood value. A second interleaver interleaves the channel value to generate an interleaved channel value. A second SOVA decoder generates a second path reliability value from an interleaved parity symbol, the second a priori likelihood value, and the interleaved channel value. A second decorrelation unit generates a second extrinsic symbol reliability value by decorrelating the interleaved channel value and the second a priori likelihood value from the second path reliability value. A second symbol reliability saturation unit saturates the second extrinsic symbol reliability value to generate a second saturated extrinsic symbol reliability value. A first de-interleaver de-interleaves the second saturated extrinsic symbol reliability value to generate the first a priori likelihood value. A second de-interleaver de-interleaves the second extrinsic symbol reliability value to generate a decoded message. Additionally, the path reliability value are saturated. Advantages include simplified hardware implementations having improved BER characteristics and faster convergence, requiring fewer decoding iterations to generate a result.

    摘要翻译： 该装置包括从信道值，奇偶校验符号和第一先验似然值产生第一路径可靠性值的第一SOVA解码器。 第一解相关单元通过从路径可靠度值去除相关的信道值和第一先验似然值来产生第一非本征符号可靠性值。 第一符号可靠性饱和单元饱和第一外部符号可靠性值以产生第一饱和外部符号可靠性值。 第一交织器交织第一饱和外在符号可靠性值以产生第二先验似然值。 第二交织器交织信道值以产生交织的信道值。 第二SOVA解码器从交织的奇偶校验符号，第二先验似然值和交织的信道值产生第二路径可靠性值。 第二去相关单元通过从第二路径可靠性值去除相关的交织信道值和第二先验似然值来产生第二非本征符号可靠性值。 第二符号可靠性饱和单元饱和第二外部符号可靠性值以产生第二饱和外部符号可靠性值。 第一解交织器对第二饱和外部符号可靠性值进行解交织以产生第一先验似然值。 第二解交织器对第二非本征符号可靠性值进行解交织以产生解码消息。 此外，路径可靠性值饱和。 优点包括具有改进的BER特性和更快收敛的简化的硬件实现，需要较少的解码迭代来产生结果。

    DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD FOR DEEP NEURAL NETWORK MODEL
    99.
    发明公开
    DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD FOR DEEP NEURAL NETWORK MODEL 审中-公开

    公开(公告)号：US20240204804A1

    公开(公告)日：2024-06-20

    申请号：US18522242

    申请日：2023-11-29

    申请人： Industrial Technology Research Institute

    发明人： Yu-Chih Huang ,  Li-Yang Tseng

    IPC分类号： H03M13/27 ,  H03M13/00 ,  H04L1/00

    CPC分类号： H03M13/27 ,  H03M13/6577 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0071

    摘要： A data processing method for a DNN model includes: reading weights of transmission data; quantizing each weight into bits sequentially including first, second, third, and fourth-type bits; sequentially interleaving the first-type bit into a first bit set; sequentially interleaving each second-type bit into second bit sets and reading a second compression rate of each second bit set in response to the compressible second bit sets; interleaving the third-type bit into a third bit set and reading a third compression rate of the third bit set in response to the compressible third bit set; compressing each second bit set with the second compression rate, and compressing the third bit set with the third compression rate; sequentially coding the first bit set, each compressed second bit set, and the compressed third bit set to generate first encoded data corresponding to the transmission data; transmitting the first encoded data to an external device.

    Low latency decoder
    100.
    发明授权
    Low latency decoder 有权

    公开(公告)号：US11929761B1

    公开(公告)日：2024-03-12

    申请号：US17938854

    申请日：2022-10-07

    申请人： Seagate Technology LLC

    发明人： Bengt Anders Ulriksson

    IPC分类号： H03M13/00 ,  H03M13/11

    CPC分类号： H03M13/1131 ,  H03M13/1125 ,  H03M13/6577

    摘要： Systems and methods are disclosed for implementing a low latency decoder. In certain embodiments, an apparatus may comprise decoder configured decode a codeword of bits, including: a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to the edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword; the edge combiner configured to generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors, and provide the plurality of output message vectors to the plurality of check node vectors simultaneously; a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.