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公开(公告)号：US20220197742A1
公开(公告)日：2022-06-23
申请号：US17694321
申请日：2022-03-14
Applicant: Seagate Technology, LLC
Inventor： Zheng Wang , Ara Patapoutian , Bengt Anders Ulriksson
Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.
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2.发明申请公开(公告)号：US20200241959A1
公开(公告)日：2020-07-30
申请号：US16259346
申请日：2019-01-28
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Ara Patapoutian , Bengt Anders Ulriksson
Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.
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公开(公告)号：US11720445B2
公开(公告)日：2023-08-08
申请号：US17694321
申请日：2022-03-14
Applicant: Seagate Technology, LLC
Inventor： Zheng Wang , Ara Patapoutian , Bengt Anders Ulriksson
CPC classification number: G06F11/1068 , G06F11/008 , G11C11/5642 , H03M13/1111
Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a codeword of the memory: obtaining at least three read values of the codeword; calculating a signal counts metric value from the at least three reads; computing an optimal reference voltage offset from the signal counts metric and a correlation between optimal reference voltage offsets and a signal counts metric associated with the memory; determining a new center read reference voltage based on a current center reference voltage and the optimal reference voltage offset and performing at least one subsequent read of the codeword following the decoding failure utilizing the new center read reference voltage.
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公开(公告)号：US20210089397A1
公开(公告)日：2021-03-25
申请号：US17115940
申请日：2020-12-09
Applicant: Seagate Technology, LLC
Inventor： Zheng Wang , Ara Patapoutian , Bengt Anders Ulriksson
Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.
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公开(公告)号：US10891189B2
公开(公告)日：2021-01-12
申请号：US16259346
申请日：2019-01-28
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Ara Patapoutian , Bengt Anders Ulriksson
Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.
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Patent Agency Ranking
公开(公告)号：US11996862B2
公开(公告)日：2024-05-28
申请号：US17930310
申请日：2022-09-07
Applicant: Seagate Technology LLC
Inventor： Bengt Anders Ulriksson , Ara Patapoutian
CPC classification number: H03M13/1111 , G06F9/546 , H03M13/611
Abstract: Systems and methods are disclosed for implementing a high performance decoder. In certain embodiments, an apparatus may comprise a decoder circuit configured to decode a codeword of bits, including: a check node processor configured to provide a plurality of check to variable (c2v) messages to a variable node processor in parallel, the plurality of c2v messages including log likelihood ratio (LLR) data related a parity sum of multiple bits of the codeword; the variable node processor configured to generate a decision vector based on the plurality of c2v messages; and a convergence checker circuit configured to determine whether the codeword has been decoded based on the decision vector and output decoded data when the codeword has been decoded.
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公开(公告)号：US11929761B1
公开(公告)日：2024-03-12
申请号：US17938854
申请日：2022-10-07
Applicant: Seagate Technology LLC
Inventor： Bengt Anders Ulriksson
CPC classification number: H03M13/1131 , H03M13/1125 , H03M13/6577
Abstract: Systems and methods are disclosed for implementing a low latency decoder. In certain embodiments, an apparatus may comprise decoder configured decode a codeword of bits, including: a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to the edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword; the edge combiner configured to generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors, and provide the plurality of output message vectors to the plurality of check node vectors simultaneously; a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.
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公开(公告)号：US11233528B1
公开(公告)日：2022-01-25
申请号：US17022549
申请日：2020-09-16
Applicant: Seagate Technology LLC
Inventor： Ivana Djurdjevic , Ara Patapoutian , Deepak Sridhara , Bengt Anders Ulriksson , Jeffrey John Pream
IPC: H03M13/11
Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.
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公开(公告)号：US20240080043A1
公开(公告)日：2024-03-07
申请号：US17930310
申请日：2022-09-07
Applicant: Seagate Technology LLC
Inventor： Bengt Anders Ulriksson , Ara Patapoutian
CPC classification number: H03M13/1111 , G06F9/546 , H03M13/611
Abstract: Systems and methods are disclosed for implementing a high performance decoder. In certain embodiments, an apparatus may comprise a decoder circuit configured to decode a codeword of bits, including: a check node processor configured to provide a plurality of check to variable (c2v) messages to a variable node processor in parallel, the plurality of c2v messages including log likelihood ratio (LLR) data related a parity sum of multiple bits of the codeword; the variable node processor configured to generate a decision vector based on the plurality of c2v messages; and a convergence checker circuit configured to determine whether the codeword has been decoded based on the decision vector and output decoded data when the codeword has been decoded.
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10.发明授权公开(公告)号：US11301323B2
公开(公告)日：2022-04-12
申请号：US17115940
申请日：2020-12-09
Applicant: Seagate Technology, LLC
Inventor： Zheng Wang , Ara Patapoutian , Bengt Anders Ulriksson
Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.
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