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    CDMA rake receiver with sub-chip resolution
    91.
    发明授权
    CDMA rake receiver with sub-chip resolution 失效
    CDMA耙式接收机具有子芯片分辨率

    公开(公告)号：US5648983A

    公开(公告)日：1997-07-15

    申请号：US427519

    申请日：1995-04-24

    申请人： Zoran Kostic ,  Gordana Pavlovic

    发明人： Zoran Kostic ,  Gordana Pavlovic

    IPC分类号： H03H21/00 ,  H04B1/7075 ,  H04B1/7093 ,  H04B1/7115 ,  H04B1/707

    CPC分类号： H03H21/0012 ,  H04B1/7115 ,  H04B1/70757 ,  H04B1/7093

    摘要： A rake receiver for use in direct-sequence code-division multiple-access communication systems employs a novel channel estimator capable of resolving multipath components spaced closer than a chip interval of the direct-sequence signature sequence. The estimator utilizes a constrained iterative deconvolution technique which employs projection onto convex sets (POCS). In a matched filter rake receiver embodiment, the delay T.sub.SC between two taps of a delay line is smaller than the duration T.sub.C of a chip of pseudo-random sequence. A rake receiver constructed in this manner is capable of detecting signals that have propagated through multipath channels and that have path components spaced closer than one chip of the signal sequence (i.e. closer than the inverse of the signal bandwidth).

    摘要翻译： 用于直接序列码分多址通信系统的瑞克接收机采用新颖的信道估计器，其能够分辨距离直接序列签名序列的码片间隔更近的多径分量。 估计器利用对凸集（POCS）进行投影的约束迭代去卷积技术。 在匹配滤波器耙式接收机实施例中，延迟线的两个抽头之间的延迟TSC小于伪随机序列码片的持续时间TC。 以这种方式构造的耙式接收机能够检测已经通过多径信道传播并且具有比信号序列的一个码片更靠近的路径分量（即比信号带宽的倒数更近）的信号。

    METHOD AND APPARATUS FOR REDUCING THE PROCESSING RATE OF A CHIP-LEVEL EQUALIZATION RECEIVER
    94.
    发明申请
    METHOD AND APPARATUS FOR REDUCING THE PROCESSING RATE OF A CHIP-LEVEL EQUALIZATION RECEIVER 审中-公开
    用于降低芯片级均衡接收机的处理速率的方法和装置

    公开(公告)号：US20120195358A1

    公开(公告)日：2012-08-02

    申请号：US13439350

    申请日：2012-04-04

    申请人： Jung-Lin Pan

    发明人： Jung-Lin Pan

    IPC分类号： H04L27/01 ,  H04B1/06

    CPC分类号： H04B1/70757 ,  H04B1/707 ,  H04B1/7115 ,  H04B2201/70707 ,  H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

    摘要翻译： 一种用于在包括均衡器滤波器的码分多址（CDMA）接收机中执行码片级均衡（CLE）时降低处理速率的方法和装置。 由接收机的至少一个天线接收的信号以芯片速率的M倍采样。 每个样本流以码片速率被分成M个采样数据流。 优选对每个分割样本数据流执行多路径组合。 然后将样本数据流以码片速率组合成一个组合的采样数据流。 均衡器滤波器以码片速率对组合的采样流进行均衡。 通过将校正项加到由均衡器滤波器用于先前迭代的滤波器系数来调整滤波器系数。

    METHOD AND APPARATUS FOR REDUCING THE PROCESSING RATE OF A CHIP-LEVEL EQUALIZATION RECEIVER
    95.
    发明申请
    METHOD AND APPARATUS FOR REDUCING THE PROCESSING RATE OF A CHIP-LEVEL EQUALIZATION RECEIVER 失效
    用于降低芯片级均衡接收器的处理速率的方法和装置

    公开(公告)号：US20110206015A1

    公开(公告)日：2011-08-25

    申请号：US13099674

    申请日：2011-05-03

    申请人： Jung-Lin Pan

    发明人： Jung-Lin Pan

    IPC分类号： H04B7/216 ,  H04W4/00

    CPC分类号： H04B1/70757 ,  H04B1/707 ,  H04B1/7115 ,  H04B2201/70707 ,  H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

    摘要翻译： 一种在包括均衡器滤波器的码分多址（CDMA）接收机中执行码片级均衡（CLE）时降低处理速率的方法和装置。 由接收机的至少一个天线接收的信号以芯片速率的M倍采样。 每个样本流以码片速率被分成M个采样数据流。 优选对每个分割样本数据流执行多路径组合。 然后将样本数据流以码片速率组合成一个组合的采样数据流。 均衡器滤波器以码片速率对组合的采样流进行均衡。 通过将校正项加到由均衡器滤波器用于先前迭代的滤波器系数来调整滤波器系数。

    Radio signal positioning
    98.
    发明授权
    Radio signal positioning 有权
    无线电信号定位

    公开(公告)号：US07701998B2

    公开(公告)日：2010-04-20

    申请号：US10595368

    申请日：2004-10-07

    申请人： Ian Oppermann

    发明人： Ian Oppermann

    IPC分类号： H04B1/00

    CPC分类号： G01S5/06 ,  G01S5/14 ,  G01S11/02 ,  H04B1/7075 ,  H04B1/70757

    摘要： Positioning of a mobile signal transmitter. A respective distance between the transmitter and each of a plurality of sensors is determined based on a direct sequence spread spectrum signal. A transmission delay of the signal is estimated with high accuracy by, in each sensor, cross-correlating an over-sampled representation of the signal with an appropriate local spreading sequence, which contains poly-phased symbol values being different from a set of symbols in the direct sequence used to spread the transmitted signal. The local spreading sequence has a nominal chip period, which is equivalent to the chip period of the over-sampled representation of the signal.

    摘要翻译： 定位移动信号发射机。 基于直接序列扩频信号确定发射机与多个传感器中的每一个之间的相应距离。 通过在每个传感器中，通过适当的局部扩展序列将信号的过采样表示互相关，从而以高精度估计信号的传输延迟，该适当的局部扩展序列包含多个相位符号值，其不同于一组符号 用于传播信号的直接序列。 本地扩展序列具有标称码片周期，等效于信号的过采样表示的码片周期。

    Method and apparatus for reducing the processing rate of a chip-level equalization receiver
    99.
    发明申请
    Method and apparatus for reducing the processing rate of a chip-level equalization receiver 失效
    降低芯片级均衡接收机的处理速率的方法和装置

    公开(公告)号：US20070253396A1

    公开(公告)日：2007-11-01

    申请号：US11824792

    申请日：2007-07-02

    申请人： Jung-Lin Pan

    发明人： Jung-Lin Pan

    IPC分类号： H04B7/216

    CPC分类号： H04B1/70757 ,  H04B1/707 ,  H04B1/7115 ,  H04B2201/70707 ,  H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

    摘要翻译： 一种用于在包括均衡器滤波器的码分多址（CDMA）接收机中执行码片级均衡（CLE）时降低处理速率的方法和装置。 由接收机的至少一个天线接收的信号以芯片速率的M倍采样。 每个样本流以码片速率被分成M个采样数据流。 优选对每个分割样本数据流执行多路径组合。 然后将样本数据流以码片速率组合成一个组合的采样数据流。 均衡器滤波器以码片速率对组合的采样流进行均衡。 通过将校正项加到由均衡器滤波器用于先前迭代的滤波器系数来调整滤波器系数。

    Method for code-alignment for DSSS signal processing
    100.
    发明申请
    Method for code-alignment for DSSS signal processing 审中-公开
    DSSS信号处理代码对齐方法

    公开(公告)号：US20070160120A1

    公开(公告)日：2007-07-12

    申请号：US11330122

    申请日：2006-01-12

    申请人： Robert Simpson

    发明人： Robert Simpson

    IPC分类号： H04B1/00

    CPC分类号： H04B1/70757 ,  G01S19/30 ,  H04B1/7077 ,  H04B1/70775 ,  H04B2001/70706 ,  H04B2201/70715

    摘要： An embodiment generally relates to a method of processing direct-sequence spread spectrum signals for temporal alignment between a received direct sequence spread spectrum (DSSS) signal and a local reference signal. The method includes receiving the received DSSS signal with bandwidth to resolve at least N samples per code chip and de-spreading the received DSSS signal to recover an elemental waveform within the received DSSS signal for an interval greater than one code chip interval as a first processing stage. The method also includes determining a discriminator value based on the elemental waveform as a second processing stage and operating a delay-locked loop based on the discriminator value to adjust an alignment between the received DSSS signal and the local reference signal.

    摘要翻译： 一个实施方案通常涉及一种处理直接序列扩频信号以在接收到的直接序列扩频（DSSS）信号和本地参考信号之间进行时间对准的方法。 该方法包括以带宽的方式接收所接收的DSSS信号，以便每个码片分解至少N个采样，并对接收到的DSSS信号进行解扩，以便在接收到的DSSS信号中恢复大于一个码片片段间隔的元素波形作为第一处理 阶段。 该方法还包括基于元素波形确定鉴别器值作为第二处理级，并且基于鉴别器值操作延迟锁定环以调整所接收的DSSS信号与本地参考信号之间的对准。