公开(公告)号：US20050136601A1

公开(公告)日：2005-06-23

申请号：US10990903

申请日：2004-11-17

Applicant: Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

Inventor： Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/336 ,  H01L21/76

CPC classification number: H01L27/11521 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/115

Abstract: A semiconductor device having a self-aligned gate conductive layer and a method of fabricating the same are disclosed. In embodiments of the present invention, a plurality of field isolation patterns are formed on a semiconductor substrate to define a plurality of active regions in the semiconductor substrate. The density of the field isolation patterns is then increased by, for example, a thermal annealing process. A plurality of gate insulation patterns are then formed on respective of the active regions. A plurality of first conductive patterns are then formed on respective of the gate insulation patterns.

Abstract translation: 公开了具有自对准栅极导电层的半导体器件及其制造方法。 在本发明的实施例中，在半导体衬底上形成多个场隔离图案以在半导体衬底中限定多个有源区。 然后通过例如热退火工艺增加场隔离图案的密度。 然后在相应的有源区上形成多个栅极绝缘图案。 然后在相应的栅极绝缘图案上形成多个第一导电图案。

公开(公告)号：US20050041477A1

公开(公告)日：2005-02-24

申请号：US10918966

申请日：2004-08-16

Applicant: Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

Inventor： Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

IPC: G11C16/04 ,  G11C7/14 ,  G11C16/02 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: G11C7/14 ,  G11C16/16

Abstract: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.

Abstract translation: 用于擦除具有包括主单元阵列区域的单元阵列区域，在主单元阵列区域的第一侧上的第一虚设单元阵列区域和第二虚拟单元阵列区域的集成电路存储器件的方法， 提供主单元阵列区域。 第一擦除电压被施加到主单元阵列区域中的多个主控制栅电极。 多个主控制栅极包括与第一虚设单元阵列区域相邻的第一最外侧主控制栅电极和与第二虚设单元阵列区域相邻的第二最外侧主控制栅电极。 第二擦除电压被施加到主单元阵列区域中的集成电路基板。 第二擦除电压大于第一擦除电压。 第三擦除电压被施加到与第一最外面的主控制栅电极相邻的第一内部虚拟控制栅电极和与第二最外面的主控制栅电极相邻的第二内部虚拟控制栅电极。 第三擦除电压小于第二擦除电压。 还提供了相关设备。

公开(公告)号：US06753572B2

公开(公告)日：2004-06-22

申请号：US10189075

申请日：2002-07-02

Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Yong-Sik Yim

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Yong-Sik Yim

IPC: H01L29792

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28282 ,  H01L29/518 ,  H01L29/792

Abstract: A floating trap type non-volatile memory device and fabrication method thereof are provided. The floating trap type device comprises a substrate, a gate electrode formed on the substrate. A charge storage layer is interposed between the substrate and the gate electrode. A tunneling layer is interposed between the substrate and charge storage layer. The charge storage layer comprises a material having a narrower band gap than silicon nitride. The charge storage layer preferably formed of tetrahedral amorphous carbon. The potential barrier between the charge storage layer and the tunneling layer is increased by using the tetrahedral amorphous carbon as the charge storage layer. Therefore, the charge retention characteristic of the floating trap type device is improved.

Abstract translation: 提供了一种浮动阱型非易失性存储器件及其制造方法。 浮动阱型器件包括衬底，形成在衬底上的栅电极。 电荷存储层介于基板和栅电极之间。 在衬底和电荷存储层之间插入隧穿层。 电荷存储层包括具有比氮化硅更窄的带隙的材料。 电荷存储层优选由四面体无定形碳形成。 通过使用四面体非晶碳作为电荷存储层，电荷存储层与隧道层之间的势垒增加。 因此，浮动捕获型装置的电荷保持特性得到改善。

公开(公告)号：US06551181B2

公开(公告)日：2003-04-22

申请号：US09944704

申请日：2001-08-31

Applicant: Chang Hyun Lee

Inventor： Chang Hyun Lee

IPC: B23F2103

CPC classification number: B24D7/06 ,  B24B55/102

Abstract: An abrasive wheel to grind or cut a variety of materials comprising a core part fixed to a tool transmitting motive power and long tips and short tips alternately attached on the base surface of a shank around the core part. The tips are arranged to cover the base surface with space therebetween at predetermined intervals along the circumference of the shank.

Abstract translation: 一种用于研磨或切割各种材料的研磨轮，其包括固定到传递动力的工具的芯部件和长的尖端以及交替地附接在芯部的芯部的基部表面上的短尖端。 尖端布置成沿着柄的圆周以预定间隔覆盖基部表面，其间具有空间。

公开(公告)号：USD466912S1

公开(公告)日：2002-12-10

申请号：US29132172

申请日：2000-11-03

Applicant: Chang Hyun Lee

Designer： Chang Hyun Lee

公开(公告)号：USD463965S1

公开(公告)日：2002-10-08

申请号：US29142064

申请日：2001-05-17

Applicant: Chang Hyun Lee ,  Joon Ho Chang

Designer： Chang Hyun Lee ,  Joon Ho Chang

公开(公告)号：USD447496S1

公开(公告)日：2001-09-04

申请号：US29128295

申请日：2000-08-22

Applicant: Chang Hyun Lee ,  Jong Moo Kang

Designer： Chang Hyun Lee ,  Jong Moo Kang

公开(公告)号：US6156263A

公开(公告)日：2000-12-05

申请号：US77906

申请日：1998-06-04

Applicant: Sang Bok An ,  Joon Yang Chung ,  Dae Saeng Kim ,  Chang Hee Yim ,  Byeong Og You ,  Hyeon Soo Choi ,  Wang Yeol Seo ,  Chang Hyun Lee

Inventor： Sang Bok An ,  Joon Yang Chung ,  Dae Saeng Kim ,  Chang Hee Yim ,  Byeong Og You ,  Hyeon Soo Choi ,  Wang Yeol Seo ,  Chang Hyun Lee

IPC: C21C7/00 ,  C21C7/10

CPC classification number: C21C7/10

Abstract: A molten steel refining apparatus and a method therefor, in which the carbon component of molten steel can be easily removed, the temperature drop of molten steel can be effectively reduced, and a stable operation is realized. The apparatus for refining molten steel for manufacturing ultra low carbon steel includes an RH vacuum-degassing device consisting of a vessel and a snorkel composed of an up-leg and a down-leg. The apparatus further includes a plurality of gas injection lance nozzles each consisting of an inner tube and an outer tube, and installed on the side wall of the vessel of the RH vacuum-degassing device so as to inject gas toward molten steel within the vessel. The inner tube includes a throat for forming a jet stream of super-sonic velocity, and the outer tube injects cooling gas for cooling the inner tube.

Abstract translation: PCT No.PCT / KR96 / 00264 Sec。 371日期：1998年6月4日 102（e）1998年6月4日PCT 1996年12月30日PCT PCT。 出版物WO98 / 15664 日期：1998年04月16日一种能够容易地除去钢水的碳成分的钢水精炼装置及其制造方法，可以有效地降低钢水的温度下降，实现稳定的运转。 用于精炼用于制造超低碳钢的钢水的设备包括由容器和由上腿和下腿组成的浮潜的RH真空脱气装置。 该装置还包括多个气体喷射喷枪喷嘴，每个喷嘴喷枪喷嘴各自由内管和外管组成，并且安装在RH真空脱气装置的容器的侧壁上，以将气体注入容器内的钢水。 内管包括用于形成超声速喷射流的喉部，外管注入用于冷却内管的冷却气体。

公开(公告)号：US10263009B2

公开(公告)日：2019-04-16

申请号：US15722216

申请日：2017-10-02

Applicant: Chang-hyun Lee ,  Jin-taek Park ,  Young-woo Park

Inventor： Chang-hyun Lee ,  Jin-taek Park ,  Young-woo Park

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/78 ,  H01L29/10 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width.

公开(公告)号：US09773796B2

公开(公告)日：2017-09-26

申请号：US14640784

申请日：2015-03-06

Applicant: Chang Hyun Lee ,  Jin-Kyu Kim

Inventor： Chang Hyun Lee ,  Jin-Kyu Kim

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11541

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11573

Abstract: A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided.