公开(公告)号：US20040140884A1

公开(公告)日：2004-07-22

申请号：US10754259

申请日：2004-01-09

Applicant: Microchip Technology Inc.

Inventor： William F. Gallagher III ,  Ronald Salesky ,  Shinichiro Inui ,  Riccardo Benedetti ,  Samuel Alexander ,  Lee R. Furey ,  Youbok Lee

IPC: H04Q005/22

CPC classification number: G06K7/10039 ,  G06K7/0008

Abstract: Arbitration of multiple transponders, such as RFID tags, occurs in an interrogation field. The arbitration process is custom-tailored for individual applications, under software control, by the transponder reader or tag reader. Different wake-up slots are calculated for each tag during successive transmission cycles based upon the tag ID and the transmission cycle number. The tag reader may also send a special command to a tag to read its data and cause the tag to become decoupled from the environment. The tags may be selectively placed in either a tag-talk-first mode or a reader-talk-first mode. Furthermore, the tag reader may send a special fast read command to the tag which includes a read request and at least one parameter of the read request.

Abstract translation: 多个转发器（如RFID标签）的仲裁发生在询问领域。 仲裁过程是由应答程序读取器或标签读取器在软件控制下针对各个应用程序进行定制的。 基于标签ID和传输周期数，在连续传输周期期间针对每个标签计算不同的唤醒时隙。 标签读取器还可以向标签发送特殊命令以读取其数据并使标签与环境分离。 标签可以选择性地放置在标签通话第一模式或读取器通话第一模式中。 此外，标签读取器可以向包括读取请求和读取请求的至少一个参数的标签发送特殊的快速读取命令。

公开(公告)号：US20250060901A1

公开(公告)日：2025-02-20

申请号：US18938806

申请日：2024-11-06

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F3/06

Abstract: A method for gather/scatter operations in a vector processor includes: (a) checking for a read port start signal and when received setting an increment count to zero; (b) initiating a memory read using a port's address register, and setting the increment count to increment count+1; (c) incrementing the port's address register by a port's stride register; (d) checking to see if the increment count is greater than or equal to a port's length register and when not so proceeding to (b); and (e) checking to see if the increment count is greater than or equal to a port's length register and when so proceeding to (a).

公开(公告)号：US12223322B2

公开(公告)日：2025-02-11

申请号：US17852304

申请日：2022-06-28

Applicant: Microchip Technology Inc.

Inventor： Aaron Severance ,  Jonathan W. Greene ,  Joel Vandergriendt

IPC: G06F9/30

Abstract: A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.

公开(公告)号：US12014068B2

公开(公告)日：2024-06-18

申请号：US17671423

申请日：2022-02-14

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0619 ,  G06F3/0673

Abstract: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.

公开(公告)号：US11892955B2

公开(公告)日：2024-02-06

申请号：US17741282

申请日：2022-05-10

Applicant: Microchip Technology Inc.

Inventor： Sanjay Goyal ,  Larrie Simon Carr ,  Patrick Bailey

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4221

Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

公开(公告)号：US11881775B2

公开(公告)日：2024-01-23

申请号：US17244882

申请日：2021-04-29

Applicant: Microchip Technology Inc.

Inventor： Jason Rabb

IPC: H02M3/158 ,  H04Q1/28

CPC classification number: H02M3/158 ,  H04Q1/28

Abstract: A system and method for generating a low supply voltage and a high supply voltage from an input voltage, wherein the dependency of the high supply voltage magnitude on the magnitude of the input voltage is removed and the resulting high supply voltage magnitude is a multiple of the low supply voltage magnitude. The low supply voltage and the high voltage may be implemented in a power converter of a communication system comprising a plurality of subscriber line interface circuits (SLICs).

公开(公告)号：US11782871B2

公开(公告)日：2023-10-10

申请号：US17701582

申请日：2022-03-22

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. Norrie

IPC: G06F15/80

CPC classification number: G06F15/8061

Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

公开(公告)号：US20230318934A1

公开(公告)日：2023-10-05

申请号：US18116293

申请日：2023-03-01

Applicant: Microchip Technology Inc.

Inventor： Steven Scott GORSHE ,  Winston Mok

IPC: H04L45/00 ,  H04L69/22 ,  H04L41/34

CPC classification number: H04L41/34 ,  H04L45/34 ,  H04L69/22

Abstract: A system and method for performing rate adaptation of sub1G packet-oriented client signals for transmission over a Metro Transport Network (MTN) by forming a 64B/66B-encoded client signal from individual client packets of the sub1G packet-oriented client signal and the idle blocks within an inter-packet gap (IPG), inserting thread operations, administration and maintenance (ThOAM) overhead to generate a 64B/66B-encoded client thread signal, performing an idle mapping procedure (IMP) to generate a rate adapted 64B/66B-encoded client thread signal, defining a plurality of pseudo-Ethernet packets in an MTN path, defining a thread channel within the plurality of pseudo-Ethernet packets and mapping the rate adapted 64B/66B-encoded client thread signal into the defined thread channel within the plurality of pseudo-Ethernet packets to generate an MTN path signal for transmission to an intermediate node or a sink mode.

公开(公告)号：US11736065B2

公开(公告)日：2023-08-22

申请号：US17884889

申请日：2022-08-10

Applicant: Microchip Technology Inc.

Inventor： Peter Meyer ,  Kamran Rahbar

IPC: H03B5/36 ,  H03K19/173 ,  H03K3/017 ,  H03B5/04

CPC classification number: H03B5/36 ,  H03B5/04 ,  H03K3/017 ,  H03K19/1737

Abstract: A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.

公开(公告)号：US20230113151A1

公开(公告)日：2023-04-13

申请号：US17884889

申请日：2022-08-10

Applicant: Microchip Technology Inc.

Inventor： Peter Meyer ,  Kamran Rahbar

IPC: H03B5/36 ,  H03B5/04 ,  H03K3/017 ,  H03K19/173

Abstract: A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.