公开(公告)号：US07951714B2

公开(公告)日：2011-05-31

申请号：US12706108

申请日：2010-02-16

申请人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： H01L21/44

CPC分类号： C25D5/02 ,  Y10T428/24331 ,  Y10T428/24917

摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

摘要翻译： 公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料 没有接缝和/或空隙。 此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

公开(公告)号：US07892899B2

公开(公告)日：2011-02-22

申请号：US12244944

申请日：2008-10-03

申请人： Haining S. Yang ,  Henry K. Utomo ,  Judson R. Holt

发明人： Haining S. Yang ,  Henry K. Utomo ,  Judson R. Holt

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/26533 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/045

摘要： A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.

摘要翻译： 一种混合取向基片的制造方法，其特征在于：（1）使基底半导体衬底的一部分露出的被掩膜的表面半导体层的水平外延增强; 和（2）基底半导体衬底的暴露部分的垂直外延增加。 所得到的表面半导体层和外延表面半导体层与不与基底半导体衬底垂直的界面邻接。 该方法还包括通过表面半导体层和外延表面半导体层注入电介质形成离子，以提供将表面半导体层和外延表面半导体层与基底半导体衬底分离的掩埋电介质层。

公开(公告)号：US20100252881A1

公开(公告)日：2010-10-07

申请号：US12814930

申请日：2010-06-14

申请人： David M. Onsongo ,  Werner Rausch ,  Haining S. Yang

发明人： David M. Onsongo ,  Werner Rausch ,  Haining S. Yang

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

摘要翻译： 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度 导体。

公开(公告)号：US20100187636A1

公开(公告)日：2010-07-29

申请号：US12754939

申请日：2010-04-06

申请人： Haining S. Yang ,  Siddhartha Panda

发明人： Haining S. Yang ,  Siddhartha Panda

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.

摘要翻译： 提供半导体结构及其制造方法，其中对nFET和pFET器件实现应变增强。 特别地，本发明提供了用于更强应变增强和缺陷减少的至少一个无间隔型FET。 至少一个无衬垫FET可以是pFET，nFET或其组合，其中无间隙pFET是特别优选的，因为pFET通常制造成具有比nFET更大的宽度。 至少一个无间隔FET允许提供比包括具有间隔物的FET的现有技术结构更靠近器件沟道的应力诱导衬垫。 实现了无间隔FET，而不会不利地影响相应的硅化物源极/漏极扩散触点的电阻，其不会侵入无间隔FET的下方。

公开(公告)号：US20100096673A1

公开(公告)日：2010-04-22

申请号：US12643482

申请日：2009-12-21

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成：在栅极上的第一层和栅极上的第二层，具有间隔物，与栅极相邻的源极和漏极区域，栅极上的硅化物和源极和漏极区域; 在由成形步骤导致的结构上设置应力层; 在应力层上设置绝缘层; 去除绝缘层的部分以暴露应力层的顶表面; 去除应力层的顶表面和其它部分和间隔物的部分以形成沟槽，然后将合适的应力材料设置到沟槽中。

公开(公告)号：US07666721B2

公开(公告)日：2010-02-23

申请号：US11308292

申请日：2006-03-15

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

公开(公告)号：US20100038705A1

公开(公告)日：2010-02-18

申请号：US12190109

申请日：2008-08-12

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Haining S. Yang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28026 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method.

摘要翻译： 半导体结构和用于制造半导体结构的方法在诸如场效应晶体管结构的场效应结构内的与栅电极相邻的间隔物之下提供底切。 可以完全或不完全地覆盖插入在间隔物和半导体衬底之间的区域的底切部被栅极电介质填充。 与栅极和半导体衬底相比，栅极电介质具有比间隔物和半导体衬底之间更大的厚度。 可以使用顺序替换栅极电介质和栅极电极法制造半导体结构。

公开(公告)号：US20100019322A1

公开(公告)日：2010-01-28

申请号：US12178326

申请日：2008-07-23

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/72 ,  H01L21/76 ,  G06F17/50

CPC分类号： H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/78654

摘要： A semiconductor device and method is provided that has a stress component for increased device performance. The method integrates a stress material into a trench used typically for an isolation structure. The method includes forming an isolation trench through a SOI layer and an underlying BOX layer. The method further includes filling the isolation trench with stress material having characteristics different than the BOX layer.

摘要翻译： 提供了具有用于增加器件性能的应力分量的半导体器件和方法。 该方法将应力材料集成到通常用于隔离结构的沟槽中。 该方法包括通过SOI层和底层BOX层形成隔离沟槽。 该方法还包括用具有不同于BOX层的特征的应力材料填充隔离沟槽。

公开(公告)号：US07635899B2

公开(公告)日：2009-12-22

申请号：US11622057

申请日：2007-01-11

申请人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

发明人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

IPC分类号： H01L27/092

CPC分类号： H01L21/823878 ,  H01L21/76227 ,  H01L21/76237

摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.

摘要翻译： 公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。 衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。 硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。 在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

公开(公告)号：US07635620B2

公开(公告)日：2009-12-22

申请号：US11306745

申请日：2006-01-10

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成：在栅极上的第一层和栅极上的第二层，具有间隔物，与栅极相邻的源极和漏极区域，栅极上的硅化物和源极和漏极区域; 在由成形步骤导致的结构上设置应力层; 在应力层上设置绝缘层; 去除绝缘层的部分以暴露应力层的顶表面; 去除应力层的顶表面和其它部分和间隔物的部分以形成沟槽，然后将合适的应力材料设置到沟槽中。