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公开(公告)号：US20200153397A1
公开(公告)日：2020-05-14
申请号：US16740800
申请日：2020-01-13
Inventor： John Paul LESSO , Toru IDO
Abstract: The present disclosure relates to Class D amplifier circuitry comprising: an input for receiving an input signal; first and second output nodes for driving a load connected between the first and second output nodes. A first driver stage is provided for switching the first node between a first supply rail and a second supply rail, and a second driver stage is provided for switching the second node between the first supply rail and the second supply rail. The Class D amplifier circuitry also includes first driver control circuitry configured to receive a first carrier wave and control the switching of the first driver stage based in part on the first carrier wave; second driver control circuitry configured to receive a second carrier wave and control the switching of the second driver stage based in part on the second carrier wave; and a carrier wave generator configured to provide the first carrier wave and the second carrier wave. A phase shift between the first carrier wave and the second carrier wave is adjustable responsive to a mode control signal.
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公开(公告)号：US20200099388A1
公开(公告)日：2020-03-26
申请号：US16581953
申请日：2019-09-25
Inventor： John Paul LESSO
Abstract: This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.
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公开(公告)号：US20200044638A1
公开(公告)日：2020-02-06
申请号：US16504534
申请日：2019-07-08
Inventor： John Paul LESSO
Abstract: This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronise any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (SOUT) from the modulator are thus synchronised to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronised to the first clock signal.
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公开(公告)号：US20200043484A1
公开(公告)日：2020-02-06
申请号：US16050593
申请日：2018-07-31
Inventor： John Paul LESSO , César ALONSO
IPC: G10L15/20 , G10L15/22 , G06F21/32 , G10L21/0208
Abstract: A method of detecting a replay attack comprises: receiving an audio signal representing speech; identifying speech content present in at least a portion of the audio signal; obtaining information about a frequency spectrum of each portion of the audio signal for which speech content is identified; and, for each portion of the audio signal for which speech content is identified: retrieving information about an expected frequency spectrum of the audio signal; comparing the frequency spectrum of portions of the audio signal for which speech content is identified with the respective expected frequency spectrum; and determining that the audio signal may result from a replay attack if a measure of a difference between the frequency spectrum of the portions of the audio signal for which speech content is identified and the respective expected frequency spectrum exceeds a threshold level.
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公开(公告)号：US20200042288A1
公开(公告)日：2020-02-06
申请号：US16050990
申请日：2018-07-31
Inventor： John Paul LESSO , Mark MCCLOY-STEVENS
IPC: G06F7/533 , H03K19/177
Abstract: This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (SC1, SC2) respectively, and generate respective first and second PWM signals (SPWM1, SPWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (SC1) corresponds to a sum of a first and second input signals (S1, S2) and the second combined signal (SC2) corresponds to the difference between the first and second input signals (S1, S2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D1, D2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D1, D2) and provides an output signal (DOUT) based on this difference.
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Patent Agency Ranking
公开(公告)号：US20190386626A1
公开(公告)日：2019-12-19
申请号：US16552843
申请日：2019-08-27
Inventor： John Paul LESSO , Toru IDO
Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.
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公开(公告)号：US20190371340A1
公开(公告)日：2019-12-05
申请号：US15992562
申请日：2018-05-30
Inventor： John Paul LESSO , Gordon Richard MCLEOD
Abstract: A method of speaker verification comprises: comparing a test input against a model of a user's speech obtained during a process of enrolling the user; obtaining a first score from comparing the test input against the model of the user's speech; comparing the test input against a first plurality of models of speech obtained from a first plurality of other speakers respectively; obtaining a plurality of cohort scores from comparing the test input against the plurality of models of speech obtained from a plurality of other speakers; obtaining statistics describing the plurality of cohort scores; modifying said statistics to obtain adjusted statistics; normalising the first score using the adjusted statistics to obtain a normalised score; and using the normalised score for speaker verification
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公开(公告)号：US20190288704A1
公开(公告)日：2019-09-19
申请号：US16375868
申请日：2019-04-05
Inventor： John Paul LESSO
IPC: H03M3/00 , H03K21/38 , H03K3/0233 , H03M1/50
Abstract: This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (SPWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (SPWM) at a first node (304) based on the input signal (SIN) and a feedback signal (SFB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK1).
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公开(公告)号：US20190147888A1
公开(公告)日：2019-05-16
申请号：US16184644
申请日：2018-11-08
Inventor： John Paul LESSO
Abstract: In order to detect a replay attack on a voice biometrics system, a first signal from received sound is generated at a first microphone, and a second signal from the received sound is generated at a second microphone. The first and second signals are used to determine a location of an apparent source of the received sound. It is determined that the received sound may result from a replay attack if the apparent source of the received sound is diffuse.
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公开(公告)号：US20190064007A1
公开(公告)日：2019-02-28
申请号：US16105484
申请日：2018-08-20
Inventor： John Paul LESSO , Gordon James BATES
IPC: G01K7/32
Abstract: This application relates to methods and apparatus for temperature monitoring for integrated circuits, and in particular to temperature monitoring using a locked-loop circuits, e.g. FLLs, PLLs or DLLs. According to embodiments a locked-loop circuit (200, 600) includes a controlled signal timing module (201, 601), wherein the timing properties of an output signal (SOUT, SFB) are dependent on a value of a control signal and on temperature. A controller (201, 601) compares a feedback signal (SFB) output from the timing module to a reference signal (SREF) and generates a control signal (SC) to maintain a desired timing relationship. A temperature monitor (202) monitors temperature based on the value of the control signal. For FLLs and PLLs the signal timing module may be a controlled oscillator (201).
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