中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

146 records (took 0.046 seconds)

    Linear transformation accelerators
    102.
    发明授权
    Linear transformation accelerators 有权

    公开(公告)号：US10529418B2

    公开(公告)日：2020-01-07

    申请号：US16079998

    申请日：2016-02-19

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Zhiyong Li ,  R. Stanley Williams

    IPC: G11C13/00 ,  G11C11/56

    Abstract: Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate a linear transformation. The crossbar array has a plurality of words lines, a plurality of bit lines, and a memory cell coupled between each unique combination of one word line and one bit line, where the memory cells are programmed according to a linear transformation matrix. The plurality of word lines are to receive an input vector, and the plurality of bit lines are to output an output vector representing a linear transformation of the input vector.

    Optical phase difference calculation using analog processing
    103.
    发明授权
    Optical phase difference calculation using analog processing 有权

    公开(公告)号：US10509167B2

    公开(公告)日：2019-12-17

    申请号：US15959580

    申请日：2018-04-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Marco Fiorentino

    IPC: G02B6/12

    Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.

    Finite state machines
    105.
    发明授权
    Finite state machines 有权

    公开(公告)号：US10261487B1

    公开(公告)日：2019-04-16

    申请号：US15885193

    申请日：2018-01-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

    IPC: G05B19/045 ,  G11C15/04

    Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

    Nonvolatile memory cross-bar array
    106.
    发明授权
    Nonvolatile memory cross-bar array 有权

    公开(公告)号：US10181349B2

    公开(公告)日：2019-01-15

    申请号：US15535765

    申请日：2014-12-15

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/00 ,  G06G7/16

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

    Multiply-accumulate circuits
    107.
    发明授权
    Multiply-accumulate circuits 有权

    公开(公告)号：US10180820B2

    公开(公告)日：2019-01-15

    申请号：US15282021

    申请日：2016-09-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

    IPC: G06F7/523 ,  G06F7/544 ,  G11C13/00

    Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

    Convolution accelerators
    110.
    发明授权
    Convolution accelerators 有权

    公开(公告)号：US10042819B2

    公开(公告)日：2018-08-07

    申请号：US15280903

    申请日：2016-09-29

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Naveen Muralimanohar

    IPC: G06F15/00 ,  G06F17/14 ,  G06F17/15

    Abstract: Examples herein relate to convolution accelerators. An example convolution accelerator may include a transformation crossbar array programmed to calculate a Fourier Transformation of a first vector with a transformation matrix and a Fourier Transformation of a second vector with the transformation matrix. A circuit of the example convolution accelerator may multiply the Fourier Transformation of the first vector with the Fourier Transformation of the second vector to calculate a product vector. The example convolution accelerator may have an inverse transformation crossbar array programmed to calculate an Inverse Fourier Transformation of the product vector according to an inverse transformation matrix.

Patent Agency Ranking