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公开(公告)号：US20110316083A1
公开(公告)日：2011-12-29
申请号：US12823798
申请日：2010-06-25
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/78648
摘要： A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.
摘要翻译： 背栅式场效应晶体管（FET）包括衬底，该衬底包括位于底部半导体层顶部的掩埋电介质层顶部的顶部半导体层; 位于顶部半导体层上的前门; 位于前门下的顶部半导体层中的沟道区; 位于沟道区一侧的顶部半导体层中的源极区域和位于与源极区域相反的沟道区域侧的顶部半导体层中的漏极区域; 以及位于底部半导体层中的背栅，后栅配置成使得后栅极邻接沟道区下方的掩埋介电层，并且在源极区和漏极区之下与掩埋介电层分离距离 。
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公开(公告)号：US09105577B2
公开(公告)日：2015-08-11
申请号：US13398151
申请日：2012-02-16
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/336 , H01L21/265 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/2652 , H01L21/26586 , H01L21/76267 , H01L21/84 , H01L29/45 , H01L29/66772 , H01L29/7831 , H01L29/78648
摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.
摘要翻译： SOI衬底，半导体器件和背栅功函数调谐方法。 衬底和器件具有多个金属背栅区域，其中至少两个区域具有不同的功函数。 该方法包括在衬底上形成掩模并且注入置于衬底氧化物和衬底的体区之间的金属背栅，从而产生具有不同剂量的杂质和不同功函数的至少两个金属背栅区。 工作功能区域可以对准，使得每个晶体管具有不同的阈值电压。 当顶栅电极用作掩模时，形成在沟道区下具有第一功函数的金属背栅和源/漏区下的第二功函数。 植入物可以倾斜以相对于掩模移动功函数区域。
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103.发明授权公开(公告)号：US08853038B2
公开(公告)日：2014-10-07
申请号：US13614572
申请日：2012-09-13
IPC分类号： H01L21/336 , H01L29/66 , H01L29/786 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.
摘要翻译： 栅极堆叠形成在掩埋氧化物层上方的硅层上。 栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。 在硅层和栅叠层上形成第一氮化物层。 在第一氮化物层上形成氧化物层。 在氧化物层上形成第二氮化物层。 蚀刻第一氮化物层和氧化物层，以便形成氮化物衬垫和邻近栅叠层的氧化物衬垫。 蚀刻第二氮化物层以形成邻近氧化物衬垫的第一氮化物间隔物。 与氮化物衬垫，氧化物衬垫和第一氮化物间隔物相邻地外延形成刻面隆起的源极/漏极区。 使用第一氮化物间隔物将离子植入到刻面隆起的源极/漏极区域中。
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公开(公告)号：US08835900B2
公开(公告)日：2014-09-16
申请号：US13154677
申请日：2011-06-07
IPC分类号： H01L29/06 , H01L27/12 , H01L21/336
CPC分类号： H01L29/7841 , H01L21/8252 , H01L21/8254 , H01L21/8258 , H01L21/84 , H01L27/0605 , H01L27/10802 , H01L27/1203
摘要： A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.
摘要翻译： 一种用于制造浮体存储单元的浮体存储单元，存储器电路和方法。 浮体存储单元包括具有耦合到第二半导体的第一半导体的双层异质结。 第一半导体和第二半导体具有不同的能带隙。 浮体存储单元包括掩埋绝缘体层。 浮体存储单元包括通过至少掩埋绝缘层与双层异质结的第二半导体分离的背晶体管栅极。 浮体存储单元还包括耦合到双层异质结的第一半导体的前晶体管栅极。
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公开(公告)号：US08610233B2
公开(公告)日：2013-12-17
申请号：US13049491
申请日：2011-03-16
IPC分类号： H01L31/102
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26586 , H01L21/823814 , H01L21/823878 , H01L29/7839
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触 并且在与栅极结构的漏极侧相邻的半导体衬底上。 因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。
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公开(公告)号：US20130214356A1
公开(公告)日：2013-08-22
申请号：US13398151
申请日：2012-02-16
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/088 , H01L21/265
CPC分类号： H01L27/1203 , H01L21/2652 , H01L21/26586 , H01L21/76267 , H01L21/84 , H01L29/45 , H01L29/66772 , H01L29/7831 , H01L29/78648
摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.
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公开(公告)号：US08482078B2
公开(公告)日：2013-07-09
申请号：US13104542
申请日：2011-05-10
IPC分类号： H01L21/70
CPC分类号： H01L27/0727 , H01L21/823418 , H01L21/84 , H01L27/0629 , H01L27/1203
摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.
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公开(公告)号：US08421156B2
公开(公告)日：2013-04-16
申请号：US12823798
申请日：2010-06-25
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/66 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/78648
摘要： A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.
摘要翻译： 背栅式场效应晶体管（FET）包括衬底，该衬底包括位于底部半导体层顶部的掩埋电介质层顶部的顶部半导体层; 位于顶部半导体层上的前门; 位于前门下的顶部半导体层中的沟道区; 位于沟道区一侧的顶部半导体层中的源极区域和位于与源极区域相反的沟道区域侧的顶部半导体层中的漏极区域; 以及位于底部半导体层中的背栅，后栅配置成使得后栅极邻接沟道区下方的掩埋介质层，并且在源极区和漏极区之下与掩埋介电层分离距离 。
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公开(公告)号：US20130082306A1
公开(公告)日：2013-04-04
申请号：US13610456
申请日：2012-09-11
IPC分类号： H01L29/778
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/66772 , H01L29/7849 , H01L29/78603 , H01L29/78654
摘要： Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.
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110.发明授权公开(公告)号：US08890245B2
公开(公告)日：2014-11-18
申请号：US13570833
申请日：2012-08-09
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。
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