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公开(公告)号：US06842845B2
公开(公告)日：2005-01-11
申请号：US09792839
申请日：2001-02-23
CPC分类号： G06F17/10 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443
摘要： An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory, a core processor for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where a packetized network is used to transceive packetized data and voice.
摘要翻译： 应用专用信号处理器（ASSP）执行向量化和非向量化操作。 可以使用饱和乘法和累加操作来执行非向量化操作。 ASSP包括串行接口，缓冲存储器，用于执行数字信号处理的核心处理器，其包括精简指令集计算机（RISC）处理器和四个信号处理单元。 四个信号处理单元并行地执行数字信号处理算法，包括执行饱和乘法和累加操作。 ASSP用于电信接口设备，如网关。 ASSP非常适合于在分组化网络用于收发分组数据和语音的电信系统中处理语音和数据压缩/解压缩。
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102.发明授权Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously 失效用于指令集体系结构的方法和装置，用于同时执行主和阴影数字信号处理子指令公开(公告)号：US06748516B2
公开(公告)日：2004-06-08
申请号：US10059698
申请日：2002-01-29
IPC分类号： G06F1576
CPC分类号： G06F9/3877 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F9/3001 , G06F9/30025 , G06F9/30101 , G06F9/30138 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30192 , G06F9/381 , G06F9/382 , G06F9/383 , G06F9/3842 , G06F9/3853 , G06F9/3885 , G06F17/10
摘要： Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. Each signal processing unit of the ASSP includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. The present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction.
摘要翻译： 公开了针对数字信号处理（DSP）应用定制的专用信号处理器（ASSP）的方法，装置和指令集架构（ISA）。 单个DSP指令包括一对子指令：主DSP子指令和阴影DSP子指令。 主要和阴影DSP子指令都是在一个指令周期内执行两个操作的二进制DSP指令。 ASSP的每个信号处理单元包括基于当前数据和阴影阶段执行主DSP子指令的主阶段，以基于本地存储在信号处理单元的寄存器内的延迟数据来同时执行影子DSP子指令。 本发明通过使用单个DSP指令同时执行主DSP子指令（基于当前数据）和阴影DSP子指令（基于延迟本地存储的数据）来有效地执行DSP指令。
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103.发明授权Method and apparatus for loop buffering digital signal processing instructions 有权用于循环缓冲数字信号处理指令的方法和装置公开(公告)号：US06598155B1
公开(公告)日：2003-07-22
申请号：US09494609
申请日：2000-01-31
IPC分类号： G06F900
CPC分类号： G06F9/381
摘要： A loop buffer for storing and holding instructions executed within loops for digital signal processing. Control logic detects the beginning and ending of a loop to signal the loop buffer control logic to start instruction execution in a cyclical fashion using the instructions stored within the loop buffer. After completion of the required number of loops, the instructions in the loop buffer are overwritten with new instructions until the next loop is to be processed. The loop buffer conserves power by avoiding the fetching of instructions unnecessarily from memory.
摘要翻译： 一个循环缓冲器，用于存储和保存用于数字信号处理的循环内执行的指令。 控制逻辑检测循环的开始和结束，以使用存储在循环缓冲器中的指令以循环方式来发出循环缓冲器控制逻辑以开始指令执行。 在完成所需数量的循环后，循环缓冲区中的指令将被新指令覆盖，直到下一个循环被处理为止。 循环缓冲器通过避免从内存中不必要地取出指令来节省功率。
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104.发明授权Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types 有权具有数据转换器和对准器的处理器选择性地将数据总线的数据位耦合到加法器和乘法器功能块以执行具有灵活数据类型的指令公开(公告)号：US06557096B1
公开(公告)日：2003-04-29
申请号：US09652556
申请日：2000-08-31
IPC分类号： G06F9302
CPC分类号： G06F9/383 , G06F5/00 , G06F7/4806 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F7/57 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/381 , G06F9/3816 , G06F9/382 , G06F9/3853 , G06F9/3877 , G06F9/3885 , G06F17/10
摘要： A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of operands of the instruction set architecture. The data typer and aligner is selectively configued to align and select one of more sets of data bits from one or more data buses as operands for functional blocks of the signal processor in response to fields of an instruction.
摘要翻译： 具有指令集架构（ISA）的信号处理器，用于灵活的数据输入，置换和操作数的类型匹配。 信号处理器包括数据转换器和对准器，以支持指令集架构的操作数的灵活数据类型，置换和类型匹配。 选择性地配置数据调整器和对准器，以响应于指令的字段，将来自一个或多个数据总线的多组数据位中的一个作为对信号处理器的功能块的操作数进行选择。
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105.发明授权公开(公告)号：US06446195B1
公开(公告)日：2002-09-03
申请号：US09494608
申请日：2000-01-31
IPC分类号： G06F9302
CPC分类号： G06F9/3877 , G06F9/3001 , G06F9/30072 , G06F9/30149 , G06F9/30189 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3885 , G06F15/8015
摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.
摘要翻译： 适用于特定于信号处理器（ASSP）的指令集体系结构（ISA）适用于数字信号处理应用。 采用ASSP实现的指令集架构适用于DSP算法结构。 ISA的指令字通常为20位，但可以扩展为40位，以控制串行或并行执行的两个指令。 ISA的所有DSP指令都是在一个周期内用一个指令执行两个操作的二进制DSP指令。 优选实施例中的DSP指令或操作包括乘法指令（MULT），加法指令（ADD），也称为极值指令的最小化/最大化指令（MIN / MAX）和无操作指令（NOP） 每个都具有相关联的操作代码（“操作码”）。 本发明通过指令集架构和应用专用信号处理器的硬件架构有效地执行DSP指令。
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106.发明授权公开(公告)号：US06330660B1
公开(公告)日：2001-12-11
申请号：US09427174
申请日：1999-10-25
IPC分类号： G06F1516
CPC分类号： G06F17/10 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443
摘要： An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory, a core processor for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where a packetized network is used to transceive packetized data and voice.
摘要翻译： 应用专用信号处理器（ASSP）执行向量化和非向量化操作。 可以使用饱和乘法和累加操作来执行非向量化操作。 ASSP包括串行接口，缓冲存储器，用于执行数字信号处理的核心处理器，其包括精简指令集计算机（RISC）处理器和四个信号处理单元。 四个信号处理单元并行地执行数字信号处理算法，包括执行饱和乘法和累加操作。 ASSP用于电信接口设备，如网关。 ASSP非常适合于在分组化网络用于收发分组数据和语音的电信系统中处理语音和数据压缩/解压缩。
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